Differential Logic Back-Gate Feedback for Transistor Matching
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Solution Overview
Problem
Current integrated circuit technologies, particularly FDSOI, face challenges in maintaining transistor uniformity due to manufacturing process variability, leading to mismatches and potential malfunctions in analog electronics, where identical transistors are required for calibration, but existing calibration methods increase circuit size and cost.
Innovation Solution
A differential logic circuit design using back-gate transistors where the output signal of one cell is applied to the rear gate of the other cell, allowing for symmetrization and compensation of propagation times, reducing the impact of manufacturing variability without increasing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If known calibration approaches are used to ensure transistor uniformity, then transistor matching is improved, but circuit surface area increases
Solution Approach 1:
The patent merges the calibration function with the normal circuit operation by using the same transistor structures for both signal processing and calibration. The differential pairs and current mirrors perform their primary functions while simultaneously enabling calibration through controlled voltage application to rear gates, eliminating the need for separate calibration circuitry and reducing overall circuit area.
Solution Approach 2:
The patent implements multi-functionality by designing transistor structures with accessible rear gates that serve dual purposes: normal operation and calibration. The same differential pairs and current mirrors used for signal processing are also used for calibration activities, allowing a single circuit structure to perform multiple functions without requiring additional dedicated calibration components.
2Manufacturing precision
If known calibration approaches are used to ensure transistor uniformity, then transistor matching is improved, but overall cost increases
Solution Approach 1:
The patent combines calibration functionality with standard circuit blocks, eliminating the need for separate calibration circuits and reducing overall circuit complexity. This integration reduces manufacturing costs by minimizing the total transistor count and circuit area while maintaining calibration capability through clever use of existing structure.
Solution Approach 2:
The patent enables self-calibration where the circuit uses its own internal resources (differential pairs, current mirrors, and rear gate control) to perform calibration without requiring external calibration equipment or additional dedicated calibration transistors. The circuit calibrates itself during normal operation or initialization phases.
3Reliability
If FDSOI technology is used to reduce dopant variability, then transistor performance is improved, but process variability still causes mismatches
Solution Approach 1:
The patent changes the control parameter for threshold voltage from dopant concentration (which varies due to process variability) to rear gate voltage (which can be precisely controlled). By applying adjustable voltages to the rear gates of FDSOI transistors, the threshold voltage can be tuned to achieve matching between differential pairs and current mirrors, overcoming the limitations of dopant variability.
Solution Approach 2:
The patent implements feedback mechanisms where the output of differential pairs or current mirrors is fed back to control the rear gate voltages, creating a self-adjusting system that automatically compensates for mismatches. This feedback loop continuously monitors and corrects threshold voltage variations, ensuring precise matching despite process variability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures balanced complementary signals with reduced jitter and improved robustness to technological variations, enabling the production of stable digital circuits and oscillators with improved performance and reduced cost.
Implementation Method 1
The FDSOI technology, which does not need doping to control the threshold voltage, and which also offers a rear gate on the transistors, makes it possible to propose a calibration solution based on the control of the rear gate of the transistors.
Data Source
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AI summary
The present invention proposes a circuit (300) in logic in differential logic capable of being chained with another circuit in differential logic which comprises a first logic cell (300-1) composed of transistors with a rear gate, the first cell having at least one first input (A) to receive at least a first input signal and having an output (S) to deliver a first output signal, and a second logic cell (300-2) complementary to the first cell, composed of transistors rear gate, the second cell having as many inputs (/A) as the first cell, each input being able to receive an input signal complementary to the respective input signal of the first cell, the second cell having an output (/S ) to deliver a second output signal complementary to the first output signal of the first cell. The circuit (300) is arranged so that the first output signal (S) of the first cell is applied to the rear gate of each transistor of the second cell (300-2), and that the second output signal (/S) of the second cell is applied to the rear gate of each transistor of the first cell (300-1).