Differential Memory Architecture for Automotive Software Updates

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Solution Overview

Problem

Conventional embedded flash technologies face challenges in high update rates and reliability due to high write/erase cycles, and emerging memory solutions lack maturity and reliability, making it difficult to efficiently update software in automotive systems without significant downtime or increased costs.

Innovation Solution

A differential memory approach using two memory areas, where one area stores true data and the other complementary data, allowing for safe and reliable updates by switching between images and utilizing the memory areas as a differential read memory, enabling efficient Software Over the Air (SOTA) updates with reduced downtime and costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional embedded flash technologies are used for software updates, then update reliability is maintained, but update rates are limited due to high write/erase cycle constraints

Engineering Contradiction:
Improveupdate rateVSAvoidwrite/erase cycle reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The memory system is segmented into two independent memory areas (first and second memory areas), allowing parallel operations where one area can be read while the other is written to, thereby increasing update rates without compromising the reliability of individual memory cells

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by writing data to the second memory area while simultaneously reading from the first memory area, and vice versa. This preliminary parallel operation enables faster software updates by preparing data in advance without waiting for sequential write/erase cycles to complete

Inventive Principle:
Principle #10Preliminary action

2Productivity

If emerging memory solutions are adopted to increase update rates, then productivity improves, but reliability and maturity are compromised

Engineering Contradiction:
Improveupdate rateVSAvoidmemory solution maturity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent merges two conventional flash memory areas into a unified differential memory system that functions as a single logical memory unit. This combination enables emerging-like update performance while maintaining the proven reliability of conventional flash technology, as both memory areas use mature flash cells with guaranteed write/erase cycle lifetimes

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If a single memory area is used for storage, then device complexity is reduced, but update capability and reliability are limited

Engineering Contradiction:
Improveupdate capabilityVSAvoidmemory architecture complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The differential memory system provides multi-functionality by enabling both conventional single-memory operation and differential update operation. The same hardware architecture supports normal read/write operations and specialized update sequences, eliminating the need for separate update hardware while improving reliability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10599350B2Using a differential memory storage architecture for updating a memory area
Publication Date: 2020.03.24 INFINEON TECHNOLOGIES AG
  • US10599350B2 patent drawing
  • US10599350B2 patent drawing
  • US10599350B2 patent drawing

AI summary

A method is suggested for updating a memory comprising a first memory area and a second memory area, the method comprising the steps: (a) using a first image of data that is stored in the first memory area while writing a second image of data to the second memory area; (b) switching to using the second image of data that is stored in the second memory area; (c) writing an inverse image of the second image to the first memory area; and (d) using the first memory area and the second memory area as a differential memory. Also, a corresponding device is provided.