Differential MTP Memory Cell Integrating Reference and Latch Functions
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Solution Overview
Problem
Multi-time programmable (MTP) storage devices, such as FAMOS memory circuits, face instability due to the need for additional reference circuits, which can mismatch with the MTP memory circuit, leading to silicon area and power dissipation issues.
Innovation Solution
A differential multi-time programmable memory cell with a second-level latch cell that provides balance signals and generates sampled signals based on load and latch control signals, eliminating the need for additional reference circuits and enhancing stability, silicon area efficiency, and reducing power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an additional reference circuit is added to generate reference current signal for current-sense amplifier, then the MTP memory circuit can perform read operations, but the device complexity increases and stability deteriorates due to mismatch
Solution Approach 1:
The patent merges the reference current generation function directly into the memory cell structure by using the complementary transistor pair (first and second transistors) that form part of the memory cell itself. The first transistor provides the reference current while the second transistor provides the memory function, eliminating the need for separate reference circuits and current-sense amplifiers. This integration resolves the stability issue caused by mismatch between separate reference circuits and memory circuits.
Solution Approach 2:
The transistor pair serves multiple functions simultaneously: the first transistor acts as a reference element, the second transistor serves as the memory element, and together they provide both storage and read-out capabilities without requiring separate dedicated reference circuits. This multi-functionality reduces device complexity while maintaining operational capability.
2Ease of operation
If an additional reference circuit and current-sense amplifier are used, then read operations can be performed, but the silicon area increases
Solution Approach 1:
The patent combines the reference circuit, memory cell, and read-out functionality into a single integrated structure using the transistor pair. This eliminates the need for separate reference circuits and current-sense amplifiers, significantly reducing the silicon area required for MTP memory operation while maintaining full read capability.
Solution Approach 2:
The transistor pair is designed to perform multiple functions within a compact structure: storage, reference generation, and differential read-out. This multi-functional design achieves read operation capability without requiring additional dedicated circuits, thereby minimizing silicon area consumption.
3Ease of operation
If an additional reference circuit and current-sense amplifier are used, then read operations can be performed, but power dissipation increases
Solution Approach 1:
The patent merges the reference current generation and memory function into the same transistor pair structure. By eliminating separate reference circuits and current-sense amplifiers, the overall power consumption is reduced while maintaining the ability to perform read operations through the differential configuration of the integrated transistor pair.
Solution Approach 2:
The integrated transistor pair performs multiple functions (reference generation, storage, and read-out) simultaneously, eliminating the need for additional power-consuming circuits. This multi-functional approach achieves read capability with lower power dissipation compared to conventional separate circuit architectures.
Data Source
AI summary
A multi-time programmable memory cell has a differential multi-time programmable memory cell and a second-level latch cell. The differential multi-time programmable memory cell provides a first balance signal and a second balance signal, and the second-level latch cell receives the first balance signal and the second balance signal and provides an output signal according to the first balance signal and the second balance signal based on a first latch control signal and a second latch control signal.