Differential Analog Neural Memory Arrays for Stable Read Precision
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Solution Overview
Problem
Existing analog neural memory arrays face challenges with varying source impedance and power consumption across the array, leading to precision issues and noise susceptibility during read, program, or erase operations.
Innovation Solution
The implementation of an analog neural memory array with approximately constant source impedance across all cells and adaptive weight mapping to ensure optimal power and noise performance, achieved through the use of differential cell pairs and distributed power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional analog neural memory arrays are used, then the array can store synapsis weights, but the source impedance varies across cells leading to precision issues and noise susceptibility
Solution Approach 1:
The patent applies equipotentiality by ensuring all memory cells in the array operate at the same potential level through constant source impedance. Each cell is designed to maintain identical source impedance characteristics regardless of its position in the array, eliminating potential differences that cause precision errors and noise susceptibility. This is achieved through careful circuit design of the memory cell structure and biasing schemes.
2Power
If conventional power distribution is used, then power can be supplied to the array, but power consumption varies from bit line to bit line causing inconsistency
Solution Approach 1:
The patent applies local quality by distributing power management functions to local elements within the array. Each bit line is equipped with local power regulation circuitry that independently controls power consumption, ensuring uniform power distribution across all bit lines. This localized approach allows each column to self-regulate its power consumption, eliminating the inconsistency that would arise from centralized power distribution.
3Reliability
If weights are mapped without adaptation, then the array can function, but performance is not optimized for power and noise
Solution Approach 1:
The patent applies dynamics by implementing adaptive weight mapping that can dynamically adjust the distribution of weight values across the array based on operational conditions. The system monitors power consumption and noise levels in real-time, and dynamically remaps weights to optimize the balance between power efficiency and noise performance. This dynamic adaptation allows the array to respond to changing operational requirements and maintain optimal performance.
Solution Approach 2:
The patent applies feedback by incorporating monitoring circuits that continuously measure power consumption and noise levels across the array. These measurements are fed back to the weight mapping controller, which uses the feedback information to adjust the weight distribution strategy. The feedback loop enables the system to learn from operational conditions and continuously optimize the weight mapping to achieve the desired balance between power efficiency and noise immunity.
Data Source
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AI summary
Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W- values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W = (W+) – (W-). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W- values.