Differential Neural Memory Array for Stable Weight Storage
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Solution Overview
Problem
Existing analog neural memory arrays face challenges with varying source impedance and power consumption across the array, leading to precision issues and susceptibility to noise during read, program, or erase operations.
Innovation Solution
The implementation of an analog neural memory system with non-volatile memory cells arranged in pairs of columns, where one column stores positive weights (W+) and the other stores negative weights (W-), allowing for differential weight storage and adaptive weight mapping to maintain constant source impedance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If non-volatile memory cells are arranged in a conventional single-column structure, then the array can store weight values, but the source impedance varies across the array leading to precision issues and noise susceptibility
Solution Approach 1:
The memory array is segmented into multiple columns (first column, second column, third column, etc.) where each column stores weight values. This segmentation allows for differential pairing of columns to maintain constant source impedance while reducing noise susceptibility across the array.
2Reliability
If memory cells are arranged in differential pairs across multiple columns, then source impedance remains constant and noise susceptibility reduces, but the array complexity increases
Solution Approach 1:
The patent extracts and eliminates the need for dummy bit lines by using a differential pair structure where real bit lines are paired together. This removes the complexity of managing dummy lines while maintaining constant source impedance across all memory cells.
Solution Approach 2:
Adjacent memory cells from different columns are merged into differential pairs sharing common bit lines. This merging approach simplifies the array structure by reducing the total number of bit lines needed while maintaining constant source impedance and improving noise immunity.
3Productivity
If conventional memory array structures are used, then the implementation is simpler, but power consumption varies across bit lines reducing efficiency
Solution Approach 1:
The patent applies local quality by making each memory cell's source impedance locally constant through differential pairing. This ensures that power consumption is evenly distributed across all bit lines during read, program, and erase operations, improving overall operational efficiency.
Data Source
AI summary
Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W− values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)−(W−).