Differential Non-Volatile Memory Cell Mitigates Gate Disturb
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Solution Overview
Problem
SONOS-based non-volatile memory devices suffer from gate disturb effects during read operations, leading to gradual changes in threshold voltage and reduced data retention, which affects the reliability of memory states.
Innovation Solution
A differential configuration of non-volatile memory cells is implemented, where two memory transistors experience identical voltage exposures, allowing the bit value to be determined by measuring the relative difference in their threshold voltages, thus ignoring changes due to gate disturb and enhancing data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SONOS-based non-volatile memory devices are used, then charge storage capability is improved, but gate disturb effects occur during read operations leading to threshold voltage changes
Solution Approach 1:
The memory cell is segmented into two separate transistors (first and second transistors) instead of using a single transistor. Each transistor independently experiences the gate disturb effect, allowing the differential measurement to cancel out the threshold voltage changes caused by gate disturb while maintaining charge storage capability in the SONOS layer.
2Device complexity
If a single memory transistor is used, then device complexity is reduced, but gate disturb causes gradual threshold voltage changes affecting memory state reliability
Solution Approach 1:
A second transistor is introduced as a copy of the first transistor, both experiencing identical gate disturb effects. The differential measurement between the two transistors cancels out the common-mode threshold voltage changes, allowing reliable memory state detection despite the increased device complexity.
3Reliability
If differential configuration with two transistors is implemented, then data retention is improved by canceling gate disturb effects, but device complexity increases
Solution Approach 1:
Both transistors in the differential pair are subjected to identical voltage conditions and gate disturb effects, creating equipotential conditions for the disturb signals. This allows the differential measurement to reject the common-mode threshold voltage changes, improving data retention despite the increased structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the impact of gate disturb, maintains the integrity of bit values over time, and improves data retention by using a differential measurement to account for identical disturbances across transistors.
Implementation Method 1
charge can be stored in the silicon nitride layer of the ONO stack by a mechanism of (direct) tunneling of electrons through the bottom silicon dioxide layer (tunnel-oxide layer) from the current carrying channel to the silicon nitride layer
Implementation Method 2
a control gate which is capable to control operations on the floating gate
Data Source
Figure 1
Figure 2
Figure 3a
AI summary
A non- volatile memory cell (50, 75) on a semiconductor substrate includes a first and a second transistor (A, B). Each transistor is arranged as a memory element that includes two diffusion regions (A1, A3; A2, A3) capable of acting as either source or drain, a charge storage element (CEA, CEB) and a control gate element (CG). A channel region is located intermediate the two diffusion regions. The charge storage element is located over the channel region, the control gate element is arranged on top of the charge storage element. One diffusion region (A3) of the first transistor (A) and one diffusion region (A3) of the second transistor (B) form a common diffusion region. The other diffusion region (A1) of the first transistor (A) is connected as first diffusion region to a first bit line, the other diffusion region (A2) of the second transistor (B) is connected as- second diffusion region to a second bit line and the common diffusion region (A3) is connected to a sensing line. A method of operating this non-volatile AND memory is also demibed.