Differential Sample-and-Hold Offset Cancellation for High Bandwidth ADCs
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Solution Overview
Problem
Sample and hold circuits in analog-to-digital converters face limitations due to bandwidth dependency on the operational amplifier and inherent volatility caused by leakage currents, leading to pedestal errors and hold mode distortion, especially in deep submicron CMOS integrated circuits.
Innovation Solution
Incorporating a CMOS switch coupled to the sampling capacitor and tied to a fixed reference voltage, which allows for high bandwidth operation independent of the op-amp transconductance, and utilizing a unity gain op-amp with differential outputs for offset cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a sample and hold circuit uses a traditional op-amp configuration, then offset cancellation can be performed, but the bandwidth is limited by the op-amp transconductance
Solution Approach 1:
The circuit is divided into two independent paths: a signal path with switch S1 and sampling capacitor C1, and a reference path with switch S2 and sampling capacitor C2. This segmentation allows the reference path to handle offset cancellation independently while the signal path maintains high bandwidth operation, resolving the contradiction between bandwidth and offset cancellation capability.
Solution Approach 2:
A dedicated reference voltage source Vref is introduced as an intermediary element. This reference source provides a stable voltage level that enables offset sampling and cancellation without requiring the main op-amp to operate at high bandwidth for this function, thus decoupling the bandwidth requirement from the offset cancellation function.
2Manufacturing precision
If the hold capacitor value is increased to reduce pedestal errors, then linearity improves, but acquisition time increases and bandwidth decreases
Solution Approach 1:
The offset voltage is sampled and stored on capacitor C2 in advance during the sampling phase. This preliminary action of capturing the offset before the hold phase begins allows the hold capacitor to be optimized for linearity without compromising acquisition speed, as the offset correction is already prepared and does not require large capacitor values for fast charging.
3Measurement precision
If system calibration is performed to remove pedestal errors, then measurement precision improves, but the process requires additional time and complexity
Solution Approach 1:
The circuit performs automatic offset cancellation using internally available elements (reference voltage Vref, switches S1 and S2, and capacitors C1 and C2). The op-amp output is fed back to its own input through the reference path, creating a self-correcting mechanism that eliminates pedestal errors without requiring external calibration equipment or additional control systems.
Data Source
AI summary
In described examples, a sample and hold circuit is configured to periodically connect one input of an op-amp to a reference voltage through a switch while a second input of the op-amp is connected to an output of the op-amp. Offset cancellation is performed by storing a sampled offset on a sampling capacitor coupled to the second input of the op-amp.