Differential Sample-and-Hold Offset Cancellation for High Bandwidth
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Solution Overview
Problem
Sample and hold circuits in analog-to-digital converters face limitations due to bandwidth dependency on the operational amplifier and inherent volatility, leading to pedestal errors and hold mode distortion, especially in high-frequency applications.
Innovation Solution
Incorporating a CMOS switch coupled to the sampling capacitor and tied to a fixed reference voltage, which allows for high bandwidth operation independent of the op-amp transconductance, and implementing a differential configuration with offset cancellation by storing sampled offset on a sampling capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the sample and hold circuit uses a traditional op-amp configuration, then the circuit is simple to implement, but the bandwidth is limited by the op-amp transconductance
Solution Approach 1:
The circuit is divided into two independent paths: a sampling path with a CMOS switch that determines the bandwidth, and an op-amp path that provides buffering and offset cancellation. This segmentation allows the bandwidth to be determined by the fast CMOS switch rather than being limited by the op-amp transconductance, while keeping the overall circuit relatively simple.
Solution Approach 2:
A sampling capacitor is introduced as an intermediary element between the input signal and the op-amp. This capacitor, controlled by a CMOS switch, captures the input signal during the sampling phase and holds it during the hold phase, enabling high-bandwidth operation independent of the op-amp speed while maintaining circuit simplicity.
2Speed
If the sample and hold circuit operates in high-frequency applications, then the sampling bandwidth increases, but pedestal errors and hold mode distortion increase
Solution Approach 1:
The circuit performs preliminary offset sampling during the sampling phase by capturing the offset voltage on the sampling capacitor before the actual signal conversion. This preliminary action of storing the offset allows the circuit to compensate for it later, reducing pedestal errors and improving linearity in high-frequency applications without sacrificing bandwidth.
Solution Approach 2:
The circuit implements feedback by connecting the op-amp output back to its input, creating a unity-gain buffer configuration. This feedback mechanism, combined with offset sampling, enables the circuit to maintain low output impedance and reduce hold mode distortion while operating at high sampling bandwidths.
3Speed
If the sample and hold circuit uses a unity gain op-amp configuration, then the circuit is simple, but the input bandwidth is limited by the op-amp bandwidth
Solution Approach 1:
The input bandwidth function is segmented from the op-amp and assigned to a separate sampling path consisting of a CMOS switch and sampling capacitor. This allows the input bandwidth to be determined by the fast switching characteristics of the CMOS device rather than being constrained by the op-amp bandwidth, while the op-amp continues to provide simple unity-gain buffering.
Solution Approach 2:
The patent replaces the traditional op-amp-based bandwidth limiting mechanism with a CMOS switch-based sampling mechanism. This substitution enables high-bandwidth operation because the CMOS switch can operate at much higher frequencies than the op-amp, while the overall circuit remains relatively simple in structure.
Data Source
AI summary
In described examples, a sample and hold circuit is configured to periodically connect one input of an op-amp to a reference voltage through a switch while a second input of the op-amp is connected to an output of the op-amp. Offset cancellation is performed by storing a sampled offset on a sampling capacitor coupled to the second input of the op-amp.