Differential Output Circuit for CML-SLVS Mode Switching
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Solution Overview
Problem
Existing high-speed data transmission technologies, such as LVDS and CML, face challenges in balancing high-speed transmission with low power consumption, as they either consume high power or increase power consumption further.
Innovation Solution
A differential output circuit that integrates CML and SLVS modes, allowing for arbitrary switching between high-speed transmission in CML mode and low-power consumption in SLVS mode, using current and voltage control respectively, with shared impedances to reduce circuit complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If LVDS is used for data transmission, then transmission speed reaches about 3 Gbps, but power consumption is high and cannot be reduced further
Solution Approach 1:
The patent implements dynamic switching between CML mode and SLVS mode based on transmission requirements. The circuit can adaptively change its operating state to optimize the balance between transmission speed and power consumption, rather than being fixed in one mode.
Solution Approach 2:
The patent changes key parameters such as voltage magnitude and signal amplitude to reduce power consumption. By using smaller voltage magnitudes in SLVS mode compared to LVDS, the patent achieves lower power consumption while maintaining acceptable transmission performance.
2Speed
If CML is used to increase transmission speed above 3 Gbps, then transmission speed improves, but power consumption increases further
Solution Approach 1:
The patent enables dynamic mode switching where CML mode can be activated temporarily for high-speed bursts when needed, while defaulting to SLVS mode for normal operation to maintain lower power consumption. This dynamic adaptation resolves the contradiction between speed and power.
Solution Approach 2:
The patent employs periodic switching between CML and SLVS modes based on data transmission requirements. High-speed CML mode is activated only when necessary for transmitting large-volume data, while SLVS mode is used for regular operation, creating a periodic pattern that balances speed and power consumption.
3Speed
If switching between LVDS and CML is implemented, then both high-speed transmission and power consumption reduction are attempted, but power consumption remains high because LVDS itself requires high power
Solution Approach 1:
The patent uses SLVS mode as a more energy-efficient alternative to LVDS for normal operation. SLVS consumes less power and is used for routine data transmission, reserving the more power-intensive CML mode only for exceptional high-speed requirements, thus replacing the expensive (in terms of power) LVDS approach with a cheaper alternative.
Solution Approach 2:
The patent fundamentally changes the voltage magnitude parameter from LVDS levels to smaller SLVS levels, which directly reduces power consumption. This parameter change allows the system to operate at lower power while maintaining transmission functionality, overcoming the limitation of LVDS-based switching approaches.
4Adaptability or versatility
If separate CML and LVDS circuits are used for mode switching, then transmission mode flexibility is achieved, but device complexity increases
Solution Approach 1:
The patent merges CML and SLVS circuit functionalities into a single integrated differential output circuit. By combining the current source, voltage source, transistor pairs, and impedance elements into one unified structure that can operate in either mode, the patent reduces device complexity compared to using separate circuits for each mode.
Solution Approach 2:
The patent designs a universal differential output circuit that can perform multiple functions: operating in CML mode for high-speed transmission, switching to SLVS mode for low-power operation, and providing differential output signals. This multi-functional design eliminates the need for separate dedicated circuits for each mode, thereby reducing overall device complexity.
Data Source
AI summary
A differential output circuit has a current source, a voltage source, first paired transistors which, in a first operating mode, switch that current from the current source should be flown to which of paired output terminals, depending on logic levels of differential input signals, and is always turned off in a second operating mode, second paired transistors which, in the second operating mode, switch which of the paired output terminals should be applied with a voltage correlated with a voltage of the voltage source, depending on the logic levels of the differential input signals, and configured to be always turned off in the first operating mode, third paired transistors which, in the second operating mode, pass the current inputted into one of the paired output terminals toward a predetermined reference potential, and is always turned on in the first operating mode, and paired impedances.