Differential Output Circuit for Cross-Point Voltage Stability
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Solution Overview
Problem
Differential amplifiers in communication interfaces experience timing skew between complementary output signals, leading to a shift in the cross-point of these signals, which deteriorates data transmission quality.
Innovation Solution
The proposed output circuit includes a specific configuration of transistors and constant current units, where transistors are cross-coupled and biased to ensure that the timing of output signal changes coincides with the changes in inverted output signals, using a differential pair and constant current units to maintain signal symmetry and reduce timing skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional differential amplifier configuration is used, then the circuit structure is simple, but timing skew occurs between complementary output signals causing cross-point shift
Solution Approach 1:
The patent applies asymmetry by introducing different circuit configurations for the differential and common-mode paths. Specifically, the differential pair transistors have different gate connections than the common-mode transistors, creating asymmetric current paths that enable independent control of differential signal timing while maintaining common-mode rejection. This asymmetric design allows timing skew compensation without requiring complete symmetry in all circuit elements.
Solution Approach 2:
The patent uses an intermediary approach by introducing a common-mode feedback circuit that mediates between the differential signal paths and the output stage. This feedback mechanism acts as an intermediary that detects timing skew and adjusts the common-mode level to compensate for cross-point shifts, thereby improving data transmission quality without directly modifying the differential signal paths.
2Reliability
If terminating resistors are used in the conventional driver circuit, then signal termination is achieved, but timing skew between output signals increases
Solution Approach 1:
The patent implements feedback by introducing a common-mode feedback circuit that continuously monitors the output signals and adjusts the common-mode level accordingly. This feedback mechanism detects timing skew caused by terminating resistors and compensates for it by adjusting the common-mode voltage, thereby maintaining signal integrity while reducing timing skew between complementary output signals.
3Reliability
If input transistors are activated at different timings, then signal levels are maintained, but cross-point of output signals shifts from midpoint
Solution Approach 1:
The patent applies equipotentiality by maintaining a stable common-mode voltage level that serves as a reference potential for both differential output signals. By keeping the common-mode level constant and well-defined, the circuit ensures that even when input transistors are activated at different timings, the output signals maintain their proper levels and cross-point remains at the midpoint voltage, thereby improving both output signal level stability and cross-point voltage accuracy.
Data Source
AI summary
An output circuit includes first to fourth transistors, first and second constant current units, and a differential pair. The gates of the first and second transistors are supplied with two input signals, respectively. The drain of the first transistor is coupled to the drain of the third transistor and the gate of the fourth transistor. The drain of the second transistor is coupled to the gate of the third transistor and the drain of the fourth transistor. The first constant current unit is coupled to the sources of the third and fourth transistors. The differential pair includes two transistors, and the gates of the two transistors are coupled to the drains of the first and second transistors, respectively. The second constant current unit is coupled to the sources of the two transistors. Two output signals are output from two nodes respectively corresponding to the drains of the two transistors.