Differential Output Circuit Tuning for Second Harmonic Reduction
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Solution Overview
Problem
Power amplifiers with differential outputs often produce significant second harmonic energy, which can exceed regulatory limits and be radiated into the environment, posing challenges in compliance with electromagnetic emission regulations.
Innovation Solution
A configurable harmonic reduction circuit with unequal calibrated capacitance values is implemented between the differential output terminals and a ground reference node, using a calibration process to minimize second harmonic signal energy by compensating for routing and device mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a power amplifier with differential output is used to amplify radio frequency signals, then signal amplification is achieved, but significant second harmonic energy is generated that may exceed regulatory emission limits
Solution Approach 1:
The patent extracts and removes the harmful second harmonic energy from the differential output signal using separate harmonic reduction circuits coupled to each differential output terminal. These circuits selectively target and eliminate the second harmonic components while preserving the fundamental frequency signal, thereby resolving the contradiction between achieving signal amplification and preventing harmful harmonic emissions.
Solution Approach 2:
The patent introduces intermediary harmonic reduction circuits as mediators between the power amplifier and the output. These circuits act as intermediate stages that process the amplified signal, reducing second harmonic energy before the signal is radiated, thus allowing the amplifier to maintain its power amplification function while the intermediary structures prevent harmful emissions.
2Stability of the object's composition
If equal capacitance values are used in the harmonic reduction circuit, then circuit symmetry is maintained, but device mismatches and routing differences cannot be compensated
Solution Approach 1:
The patent deliberately introduces asymmetry by allowing the first and second harmonic reduction circuits to have different capacitance values. This asymmetric configuration enables each circuit to be optimized for its specific differential output terminal, compensating for manufacturing variations, routing differences, and device mismatches. The asymmetry resolves the contradiction by prioritizing harmonic reduction effectiveness over circuit symmetry.
Solution Approach 2:
The patent applies local quality by allowing different capacitance values in different parts of the circuit (each harmonic reduction circuit can have independently optimized capacitance). This enables each section of the circuit to be tailored to its specific requirements, compensating for local variations in routing and device characteristics, thus resolving the contradiction between overall circuit symmetry and local optimization for harmonic reduction.
3Device complexity
If a fixed capacitance circuit is used, then circuit simplicity is maintained, but adaptability to different operating conditions and devices is limited
Solution Approach 1:
The patent implements dynamic adaptability by allowing the capacitance values in the harmonic reduction circuits to be adjusted or selected from multiple options. This dynamic capability enables the circuit to adapt to different operating conditions, device variations, and frequency ranges, resolving the contradiction between maintaining simple circuit structure and achieving high adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces electromagnetic emissions at the second harmonic frequency, ensuring compliance with regulatory limits by optimizing capacitance values for each instance of the electronic system, thereby minimizing harmonic generation.
Implementation Method 1
A first configurable shunt capacitance circuit is coupled between a first differential output terminal of the differential output and a ground reference node, and a second configurable shunt capacitance circuit is coupled between a second differential output terminal of the differential output and the ground reference node
Data Source
AI summary
An electronic circuit includes a differential output circuit that produces a differential output signal at a differential output. A primary winding of a balun has a first balun terminal coupled to a first differential output terminal, and a second balun terminal coupled to a second differential output terminal. A configurable harmonic reduction circuit includes first and second configurable shunt capacitance circuits coupled between the first differential output terminal or the second differential output terminal, respectively, and a ground reference node. A control circuit receives tuning data associated with a calibrated tuning state. The tuning data indicates a first and second calibrated capacitance values, which are unequal, for the first and second configurable shunt capacitance circuits, respectively. The control circuit controls the first configurable shunt capacitance circuit to have the first calibrated capacitance value, and controls the second configurable shunt capacitance circuit to have the second calibrated capacitance value.