Differential Output Circuit With Adjustable MOS Capacitance for Slew Control

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Solution Overview

Problem

USB output circuits with different transmission speeds face issues of parasitic capacitors causing fast or slow slew rates and voltage overshoot/undershoot due to varying operation voltages, lacking an adjusting mechanism.

Innovation Solution

A signal output apparatus with two output circuits, two MOS capacitors, and two current supplying circuits, where the capacitors' capacitance is controlled by enabling/disabling current supplying circuits to match predetermined levels based on operation modes, using inverters and resistors to generate appropriate output voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If output circuits operate under different transmission speeds with different operation voltages, then transmission speed is improved, but parasitic capacitors cause voltage overshoot and undershoot

Engineering Contradiction:
Improvetransmission speedVSAvoidvoltage overshoot and undershoot
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent changes the capacitance parameter of MOS capacitors by adjusting their voltage state through current supplying circuits. Under different operation modes (first and second modes), the capacitance values are dynamically adjusted to compensate for parasitic effects at different transmission speeds, thereby resolving the voltage overshoot and undershoot issues while maintaining high-speed transmission capability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent converts the harmful parasitic capacitors into beneficial MOS capacitors that can be actively controlled. By enabling current supplying circuits to charge these capacitors appropriately, the originally harmful parasitic effects are transformed into useful capacitance that helps stabilize voltage transitions and reduce overshoot/undershoot during high-speed operation

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Ease of operation

If parasitic capacitors are present in output circuits, then circuit operation is simplified, but slew rate becomes too fast or too slow without adjustment mechanism

Engineering Contradiction:
Improvecircuit operation simplicityVSAvoidslew rate control
Core Design Contradiction:
Ease of operationVSSpeed

Solution Approach 1:

The MOS capacitors serve dual purposes: they act as parasitic capacitors during normal operation (maintaining circuit simplicity) and as adjustable capacitance elements when current supplying circuits are activated. The system self-adjusts by enabling or disabling current paths to charge the capacitors, providing slew rate control without adding complex external circuitry

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively adjusts capacitance to reduce the impact of parasitic capacitors, improving signal output performance across different speed modes by managing slew rates and voltage overshoot/undershoot.

Implementation Method 1

two MOS capacitors and two current supplying circuits... control a capacitance of each of the two MOS capacitors to be larger than a predetermined level

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11677394B2Signal output apparatus and method
Publication Date: 2023.06.13 REALTEK SEMICON CORP
  • US11677394B2 patent drawing
  • US11677394B2 patent drawing

AI summary

The present invention discloses a signal output apparatus. Each of two output circuits includes an inverter including an input terminal and an output terminal, and a resistor coupled between the output terminal and a differential output terminal. Each of MOS capacitors is coupled between the output terminals. Under a first operation mode, two current supplying circuits are disabled. The input terminals respectively receive a high and a low state input voltages and the output terminals generate a low and a high state output voltages. The capacitances become larger than a predetermined level. Under a second operation mode, one of the current supplying circuits is enabled to output a supplying current to the differential output terminal. The input terminals receive the high state input voltage. The output terminals generate the low state output voltage. The capacitances become not larger than the predetermined level.