Sample-and-Hold Circuit Using Differential Pair ON-Voltage Control
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Solution Overview
Problem
Existing sample-and-hold circuits face challenges in suppressing signal deviation due to clock feedthrough, which increases power consumption and layout area, particularly in applications like display devices.
Innovation Solution
A sample-and-hold circuit configuration that includes a differential pair of MOS transistors, a capacitor, a switch transistor, and ON-voltage control transistors, where the gate terminal of the switch transistor is coupled to a specified node of the differential pair, reducing the ON voltage and suppressing sample deviation without the need for additional circuitry or increased power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a voltage generating circuit is used to drive the switch transistor with a moderately higher ON voltage, then the sample deviation caused by clock feedthrough is suppressed, but the layout area and power consumption increase
Solution Approach 1:
The patent extracts the voltage generation function from a separate voltage generating circuit and integrates it into the differential pair structure. The first MOS transistor's gate receives the input signal while its source is connected to the second MOS transistor's gate, creating an integrated voltage generation mechanism that eliminates the need for external voltage generating circuits, thereby reducing layout area while maintaining the ability to suppress sample deviation
Solution Approach 2:
The patent merges the voltage generation function with the differential pair structure by connecting the source of the first MOS transistor to the gate of the second MOS transistor. This integration allows the differential pair to generate the necessary ON voltage internally, combining multiple functions into a single structure and eliminating separate voltage generating circuits, thus reducing both layout area and power consumption
2Measurement precision
If a voltage generating circuit is used to drive the switch transistor with a moderately higher ON voltage, then the sample deviation caused by clock feedthrough is suppressed, but the power consumption increases
Solution Approach 1:
The patent extracts the voltage generation function from a separate voltage generating circuit and integrates it into the differential pair structure. The first MOS transistor's gate receives the input signal while its source is connected to the second MOS transistor's gate, creating an integrated voltage generation mechanism that eliminates the need for external voltage generating circuits, thereby reducing layout area while maintaining the ability to suppress sample deviation
Solution Approach 2:
The patent merges the voltage generation function with the differential pair structure by connecting the source of the first MOS transistor to the gate of the second MOS transistor. This integration allows the differential pair to generate the necessary ON voltage internally, combining multiple functions into a single structure and eliminating separate voltage generating circuits, thus reducing both layout area and power consumption
Data Source
AI summary
A sample-and-hold circuit of the disclosure includes: a differential pair that includes a first MOS transistor and a second MOS transistor, in which respective source terminals of the first MOS transistor and the second MOS transistor are interconnected to a specified node, and an input signal is input to a gate terminal of the first MOS transistor; a capacitor that is coupled to a gate terminal of the second MOS transistor, and samples and holds the input signal; a switch transistor that has a source terminal coupled to the capacitor and the gate terminal of the second MOS transistor, and causes the capacitor to sample and hold the input signal upon application of a predetermined ON voltage; and an ON-voltage control transistor that couples a gate terminal of the switch transistor to the specified node when causing the input signal to be sampled and held.