Differential Pair Tail Current Switching for Low-Offset Low-Power Operation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices face challenges in operating differential pairs at both high speed with high consumption current and low speed with low consumption current without increasing the layout area, due to mismatch characteristics of MOS transistors that cause input offset voltage variations.
Innovation Solution
The semiconductor device incorporates differential pair transistors with a tail current source that allows current levels to be switched between at least two levels, using transistors with a characteristic where σ(ΔI/gm) decreases monotonously as current decreases, eliminating the hump characteristic in the weak inversion region to reduce input offset voltage variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large transistor capable of operating in both strong inversion region and weak inversion region is installed, then the circuit can operate at both high speed with high consumption current and low speed with low consumption current, but the layout area is enlarged
Solution Approach 1:
The patent applies dynamics by making the tail current switchable between at least two levels, allowing the differential pair transistors to dynamically transition between strong inversion region operation (high speed, high consumption) and weak inversion region operation (low speed, low consumption). This dynamic current control enables a single differential pair to adapt to different operation modes without requiring multiple dedicated circuits, thereby avoiding layout area enlargement while maintaining operation mode adaptability.
2Use of energy by stationary object
If differential pair transistors operate in weak inversion region with low consumption current, then power consumption is reduced, but input offset voltage increases due to mismatch characteristics
Solution Approach 1:
The patent applies parameter changes by selecting differential pair transistors with specific characteristic parameters - namely, transistors where σ(ΔI/gm) decreases monotonously with current decrease. This parameter selection ensures that as the tail current is reduced for low-power operation in the weak inversion region, the input offset voltage due to mismatch actually decreases rather than increases, thereby achieving both low power consumption and low input offset voltage simultaneously.
Data Source
AI summary
A semiconductor device configured that its differential pair is made operable in both states of high speed with a high consumption current and low speed with a low consumption current. A differential circuit includes differential pair transistors and a tail current source for supplying a tail current that is switchable so that an amount of current flowing in the differential pair transistors may be switched between at least two sates of different levels. The differential pair transistors have a characteristic that, with a decrease of currents flowing in the differential pair transistors, a value of σ(ΔI/gm) decreases monotonously, where σ denotes a standard deviation, ΔI denotes a difference of the amounts of current of the differential pair transistors, and gm denotes transconductance of the differential pair transistors.