Differential Pair Test Circuitry Without Transmission Line Loading
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Solution Overview
Problem
In high-speed wired communication circuitry, parasitic capacitance of transmission lines increases when a test circuitry is connected, leading to decreased signal transmission speed, and existing solutions fail to detect failures in circuit elements without adversely affecting signal transmission.
Innovation Solution
A semiconductor circuitry design that includes a differential transistor pair, current sources, and a test circuitry connected to the sources of the differential transistor pair, allowing for failure detection without increasing parasitic capacitance of the transmission lines by stopping current outputs and using a variable resistor to adjust gain, thereby isolating the test circuitry from the output transmission lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If test circuitry is connected to transmission lines for failure detection, then detection capability is improved, but parasitic capacitance increases and signal transmission speed decreases
Solution Approach 1:
A buffer circuit is introduced as an intermediary between the test circuitry and the transmission lines. This buffer circuit allows the test circuitry to be connected to the transmission lines for failure detection while isolating the parasitic capacitance of the test circuitry from affecting the signal transmission on the lines, thus maintaining signal transmission speed while enabling effective failure detection.
Solution Approach 2:
The circuit is divided into separate functional segments: the transmission line segment for signal communication and the test circuitry segment for failure detection. The buffer circuit acts as a boundary between these segments, allowing independent operation and preventing the test circuitry from degrading transmission performance.
2Reliability
If test circuitry is connected to transmission lines to detect failures in latter-stage circuitry, then detection coverage is improved, but parasitic capacitance of transmission lines increases
Solution Approach 1:
The buffer circuit serves as a mediator that enables the test circuitry to monitor the transmission lines and latter-stage circuitry for failures without directly loading the transmission lines. This isolation prevents the test circuitry's parasitic capacitance from degrading signal transmission while maintaining comprehensive failure detection capability.
3Measurement precision
If test circuitry is connected to transmission lines for comprehensive failure detection, then detection capability is improved, but signal transmission performance is adversely affected
Solution Approach 1:
The buffer circuit is introduced as an intermediary component that decouples the test circuitry from the transmission lines. This allows the test circuitry to be connected for comprehensive failure detection of both the differential transistor pair and latter-stage circuitry while the buffer prevents any degradation of signal transmission performance by isolating the parasitic capacitance effects.
Data Source
AI summary
A semiconductor circuitry includes a first circuitry having a differential transistor pair and a pair of current sources connected in series to the differential transistor pair, a pair of transmission lines connected to the differential transistor pair at the opposite side to the current sources, and a second circuitry, connected to a node between the differential transistor pair and the current sources, and configured to test operations of at least the differential transistor pair and a latter-stage circuity connected to the transmission lines, in the state where the current outputs of the pair of current sources are stopped.