Differential PFD Circuit for Skew-Free PLL Charge Pump Signals

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional phase-frequency detectors (PFDs) in phase-locked loops (PLLs) fail to generate true and complementary differential signals without introducing skew, which leads to errors in differential charge pumps, affecting common mode control and compatibility with industry standards.

Innovation Solution

A differential phase-frequency detector (PFD) is electrically coupled to a charge pump, comprising two differential latches and a differential AND gate, which generates true and complementary signals without the need for skew-introducing devices like clock splitters, ensuring accurate signal pairing for differential charge pumps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional phase-frequency detectors are used to generate differential signals, then signal generation is achieved, but skew is introduced between true and complement signals

Engineering Contradiction:
Improvesignal accuracyVSAvoidsignal skew
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The PFD is divided into two separate differential latches (first and second latches) that independently process reference and feedback clock signals. Each latch generates one side of the differential pair, allowing independent optimization and reducing skew between true and complement signals.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A differential AND gate is introduced as an intermediary component to combine the outputs of the two differential latches. This mediator ensures that the true and complement signals are properly aligned and skew-free by controlling the timing and synchronization of signal generation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If clock splitters are used to generate differential signals, then signal generation is achieved, but device compatibility is affected

Engineering Contradiction:
Improvedevice compatibilityVSAvoidcircuit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The functionality of clock splitters is merged into the differential latch structure itself. The latches are designed to inherently generate differential outputs without requiring external clock splitting circuits, thereby improving device compatibility while maintaining circuit integration.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If conventional PFD structures are used, then basic phase detection is achieved, but common mode control accuracy deteriorates

Engineering Contradiction:
Improvecommon mode controlVSAvoidvoltage level accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The differential PFD structure provides improved feedback to the charge pump by ensuring that true and complement signals are precisely differentiated. This enhanced feedback mechanism allows the common mode control loop to more accurately maintain proper voltage levels, improving both reliability and measurement precision.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9923565B2Differential phase-frequency detector
Publication Date: 2018.03.20 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9923565B2 patent drawing
  • US9923565B2 patent drawing
  • US9923565B2 patent drawing

AI summary

A phase-frequency detector (PFD) is electrically coupled to a charge pump of a phase-locked-loop (PLL). The PFD includes a first differential latch electrically coupled to the charge pump. The first differential latch drives a differential pair of increment signals to the charge pump in response to differential pairs of both reference clock signals and reset signals. The PFD also includes a second differential latch electrically coupled to the charge pump. The second differential latch drives a differential pair of decrement signals to the charge pump in response to differential pairs of both feedback clock signals and reset signals. The PFD also includes a differential AND gate electrically coupled to both the first differential latch and the second differential latch. The differential AND gate drives the differential pair of reset signals to both of the differential latches in response to the differential pairs of both increment signals and decrement signals.