Differential Phase Amplitude Detector Circuit Asymmetric Charging
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Solution Overview
Problem
Existing RF signal detection circuits face challenges in efficiently and accurately measuring differences in phase and amplitude between two RF signals, requiring complex calibration and lacking in simplicity, low power consumption, and small size.
Innovation Solution
A differential phase and amplitude detection circuit utilizing NMOS and PMOS transistors with a sampling capacitor, where the circuit charges or discharges based on voltage differences between the two RF signals, allowing for fast and low-power detection without the need for complex calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a differential phase and amplitude detection circuit is designed to be simple and low power, then power consumption and circuit size are reduced, but detection speed and accuracy may deteriorate
Solution Approach 1:
The circuit dynamically adjusts the charging/discharging rates of the sampling capacitor based on the voltage difference between RF signals. When V1 > V2, the capacitor charges rapidly through the NMOS transistor; when V1 < V2, it discharges through the PMOS transistor. This dynamic operation allows fast detection responses while maintaining low average power consumption, as the circuit only actively charges or discharges when voltage differences exist.
Solution Approach 2:
The detection circuit operates periodically by alternately charging and discharging the sampling capacitor in response to alternating voltage differences between the two RF signals. This periodic charge-discharge cycle enables continuous detection while allowing the circuit to reset and prepare for the next measurement cycle, maintaining both speed and energy efficiency.
2Measurement precision
If asymmetric charging/discharging current paths are used, then detection sensitivity is improved, but circuit complexity increases
Solution Approach 1:
The circuit employs asymmetric current paths for charging and discharging the sampling capacitor. The charging path uses the NMOS transistor controlled by V1, while the discharging path uses the PMOS transistor controlled by V2. This asymmetry allows the circuit to detect voltage differences in both polarities with high sensitivity, as each transistor optimally conducts in its respective direction, while maintaining relatively simple circuit topology.
Solution Approach 2:
The circuit automatically selects the appropriate current path (charging or discharging) based on the relative voltages V1 and V2 without requiring external control signals. When V1 > V2, the NMOS transistor naturally conducts to charge the capacitor; when V1 < V2, the PMOS transistor conducts to discharge it. This self-service mechanism improves detection sensitivity while avoiding complex control logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit effectively detects differences in RF signals by charging or discharging a capacitor asymmetrically, providing a simple, low-power, and compact solution for phase and amplitude measurement, improving reaction time and reducing calibration requirements.
Implementation Method 1
a sampling capacitor coupled between the first node and the second node
Implementation Method 2
an excess current sourced by the NMOS transistor and sinked by the PMOS transistor flows from the first node to the second node to charge the sampling capacitor
Data Source
AI summary
A differential phase and amplitude detector circuit is presented. Two source follower circuits respectively based on NMOS and PMOS transistors are used to charge and discharge a sampling capacitor asymmetrically to provide a measurement of phase and/or amplitude difference between two signals of a substantially same frequency. The measurement can be made in one cycle, with the charging of the sampling capacitor performed during a first half cycle where a voltage difference between the two signals is positive, and the discharging during a second half cycle where a voltage difference between the two signals is negative. Biasing of the two source follower circuits enable an excess current flow between the two transistors of the two source follower circuits beyond a biasing current of the transistors to charge the sampling capacitor during the first half cycle, and disable the excess current flow between the two transistors during the second half cycle.