Differential Bang-Bang Phase Detector for Low-Jitter MDLLs
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Solution Overview
Problem
Existing phase detectors in multiplying delay-locked loops (MDLLs) suffer from clock jitter and reference spur level issues due to non-differential designs, which affect the accuracy and stability of frequency multiplication in wireless communication systems.
Innovation Solution
A fully differential phase detecting circuit using standard digital cells, specifically a set-reset (S-R) latch topology with cross-coupled NAND gates and inverters, is implemented to compare rising edges of reference and feedback signals, eliminating offset and reducing reference spur levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a non-differential phase detector design is used, then the device complexity is reduced, but clock jitter and reference spur levels increase, degrading measurement precision
Solution Approach 1:
The patent applies asymmetry by implementing a fully differential phase detector structure where the symmetric differential configuration (with complementary S-R latches and D flip-flops) eliminates offset errors and reduces reference spur levels, thereby improving measurement precision while maintaining manageable device complexity through systematic design
2Measurement precision
If a fully differential phase detector is implemented, then measurement precision and stability are improved, but device complexity increases
Solution Approach 1:
The patent segments the fully differential phase detector into distinct functional blocks: differential S-R latches for edge detection, D flip-flops for phase comparison, and associated logic circuits. This segmentation allows each component to be optimized independently while maintaining overall precision, thereby managing device complexity through modular architecture
3Ease of manufacture
If standard digital cells are used to implement the phase detector, then ease of manufacture is improved, but measurement precision may be compromised
Solution Approach 1:
The patent employs parameter changes by carefully selecting and tuning the characteristics of standard digital cells (such as gate sizes, threshold voltages, and timing parameters) to achieve the desired phase detection precision. This allows the use of conventional manufacturing processes while maintaining high measurement accuracy through optimized cell parameters
Data Source
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AI summary
Certain aspects of the present disclosure provide fully differential phase detectors for use in delay-locked loops, for example. One example phase detecting circuit generally includes a first input for a reference signal; a second input for an input signal to be compared with the reference signal; a set-reset (S-R) latch having a set input, a reset input, a first output, and a second output, and a delay (D) flip-flop having a logic input, a clock input, a reset input, and a logic output. The first input is connected with S-R reset input, the second input is connected with S-R set input, the first S-R output is connected with the D clock input, and the second S-R output is connected with the D reset input. The logic output of the D flip-flop indicates whether the input signal is leading or lagging the reference signal.