Differential Pin Pair Layout for IC Package Cross-Talk Cancellation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As pin pitches in integrated circuit packages decrease, cross-talk or interference between differential signal pins increases, posing a challenge in maintaining signal integrity without increasing device size or reducing pin density.

Innovation Solution

The arrangement of differential signal pins in an orthogonal array with alternating orientations and the strategic placement of ground pins and vias to cancel or reduce cross-talk, along with the use of signal trace pairs and anti-pads to prevent interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If pin pitch is decreased to increase pin density, then the number of pins that can be accommodated increases, but cross-talk or interference between pins increases

Engineering Contradiction:
Improvepin densityVSAvoidcross-talk interference
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent applies asymmetry by alternating the orientation of differential signal pin pairs in a checkerboard pattern. Instead of all pin pairs having the same orientation, adjacent pin pairs are oriented at 90 degrees to each other. This asymmetric arrangement breaks the symmetry of electromagnetic field coupling between adjacent pins, thereby reducing cross-talk interference while maintaining high pin density.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent converts the harmful cross-talk interference into a beneficial cancellation effect. By arranging differential pin pairs in alternating orientations, the electromagnetic fields from adjacent pin pairs interact in a way that causes destructive interference of the unwanted coupling signals. The cross-talk that would normally be harmful is transformed into a self-cancelling phenomenon, reducing net interference.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Object-affected harmful factors

If pin pitch is increased to reduce cross-talk, then cross-talk interference decreases, but device size increases

Engineering Contradiction:
Improvecross-talk interferenceVSAvoiddevice size
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The asymmetric alternating orientation arrangement allows pins to be placed closer together without increasing device size. The cross-talk reduction is achieved through the orientation pattern rather than increased spacing, enabling compact device design while maintaining signal integrity.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent changes the orientation parameter of adjacent pin pairs from being identical to being perpendicular (90 degrees apart). This parameter change in the spatial arrangement of pins provides cross-talk reduction without requiring changes in pin pitch or device dimensions.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If conventional pin arrangement is used, then manufacturing is simpler, but signal mismatch occurs between positive and negative signal pins

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidsignal integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the pin array into two interleaved subsets: one subset with pin pairs oriented in one direction, and another subset with pin pairs oriented perpendicular to the first. This segmentation into alternating orientation groups allows each subset to maintain consistent signal characteristics while the overall pattern provides cross-talk reduction, balancing manufacturing feasibility with signal integrity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11917749B1Integrated circuit package differential pin pattern for cross-talk reduction
Publication Date: 2024.02.27 MARVELL ISRAEL (M L S L) LTD
  • US11917749B1 patent drawing
  • US11917749B1 patent drawing
  • US11917749B1 patent drawing

AI summary

An integrated circuit package, including a circuit board, signal pins extending orthogonally to the circuit board surface, and grouped into a plurality of differential signal pin pairs, each signal pin pair positioned at a vertex of an array of orthogonal rows and columns, wherein each signal pin pair includes a positive and a negative signal pin. The plurality of signal pin pairs includes a first subset of signal pin pairs wherein the positive and the negative signal pins are arranged in an orientation along a line parallel to rows of the array and a second subset of signal pin pairs in which the positive and the negative signal pins are arranged in an orientation along a line parallel to columns of the array. For each signal pin pair in one of the first and second subsets, each nearest signal pin pairs belong to another of the first and second subsets.