Differential Configuration Interface for Fast PLD Programming
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Solution Overview
Problem
Existing systems for loading configuration data into programmable logic devices are either slow due to serial single-ended signaling or consume an undesirable number of input-output pins when using parallel signaling.
Innovation Solution
A differential signaling arrangement is used to convey configuration data to programmable logic devices, which allows for high-speed data transfer without the need for a large number of input/output pins, utilizing differential signal input buffer circuitry, clock and data recovery circuitry, and error detection for reliable data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel signaling is used to load configuration data, then loading speed is improved, but the number of input-output pins consumed increases
Solution Approach 1:
The configuration data is segmented into multiple channels, with each channel carrying a portion of the data simultaneously. This allows parallel data transfer through multiple single-ended signals rather than requiring a single high-speed parallel interface, thus achieving fast loading with fewer pins.
Solution Approach 2:
The patent transitions from traditional parallel signaling (using multiple pins simultaneously) to a time-multiplexed approach where multiple data streams are transmitted over a single differential pair by encoding them in the time domain. This dimensional shift from spatial parallelism to temporal multiplexing resolves the pin count contradiction.
2Quantity of substance
If serial single-ended signaling is used to load configuration data, then pin consumption is reduced, but loading speed decreases
Solution Approach 1:
The configuration data is divided into multiple segments that are transmitted simultaneously through different channels. Each channel uses simple single-ended signaling that consumes minimal pins, while the combined throughput of all channels achieves high overall loading speed.
Solution Approach 2:
Multiple single-ended data channels are merged into a unified configuration loading system. Individually each channel is slow and pin-efficient, but when combined they achieve both high speed and low pin consumption simultaneously.
3Reliability
If thorough testing of programmable logic devices is performed, then device reliability is improved, but testing time increases
Solution Approach 1:
Configuration data is pre-loaded into the programmable logic device at high speed using the differential signaling interface before testing begins. This preliminary high-speed configuration enables subsequent thorough testing to be performed more efficiently, reducing overall testing time while maintaining reliability.
Data Source
AI summary
A programmable logic device that receives and stores configuration data in configurable random-access-memory has differential signal input buffer circuitry for receiving the configuration data from a configuration device in differential signal form at high speeds. The programmable logic device may have clock and data recovery circuitry that receives a reference clock and that generates a corresponding internal clock that is used for receiving the configuration data. Error detection circuitry may be used to detect errors occurring during data transmission. The configuration device may have a serializer that serializes parallel configuration data received from memory and differential signal output driver circuitry that provides the configuration data in differential signal form to the programmable logic device.