Differential Predriver Scaling for Low-Power Bus PHY Drivers
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Solution Overview
Problem
High-speed bus interface PHY circuits consume excessive power due to the large number of parallel driver circuits required for impedance matching and drive capability.
Innovation Solution
A low power auto-scalable differential predriver circuit that enables or disables predriver circuits based on the number or combination of driver circuit layers, using a control code to selectively activate driver slices and buffer circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If parallel layers of driver circuits are used to provide sufficient drive capability and match bus impedance, then drive capability and impedance matching are improved, but power consumption increases significantly
Solution Approach 1:
The patent implements dynamic control of predriver circuits by enabling or disabling specific predriver stages based on the number of active driver layers. The control logic dynamically adjusts which predrivers are active according to the driver configuration, allowing the system to adapt power consumption to actual operational needs rather than maintaining all predrivers in a static active state.
Solution Approach 2:
The patent changes the operational state parameter of predriver circuits from always-on to conditionally-active. By monitoring the driver layer configuration and adjusting the enable/disable state of corresponding predrivers, the system modifies the power consumption parameter while maintaining adequate drive capability for the active configuration.
2Adaptability or versatility
If multiple predriver circuits are enabled to support multiple driver layers, then drive capability is improved, but power consumption increases
Solution Approach 1:
The patent segments the predriver circuits into multiple independent controllable stages, where each predriver stage can be individually enabled or disabled. This segmentation allows the system to activate only the specific predriver stages needed for the current driver layer configuration, rather than enabling all predrivers simultaneously, thus reducing power consumption while maintaining adaptability.
Solution Approach 2:
The system dynamically adjusts the activation state of individual predriver stages based on the required driver layer configuration. The control logic responds to changes in driver configuration and selectively enables only the necessary predriver stages, providing adaptive power management that matches the actual operational requirements.
3Reliability
If all predriver circuits are continuously enabled, then signal buffering capability is maintained, but unnecessary power is consumed
Solution Approach 1:
The patent implements periodic or conditional activation of predriver circuits based on operational requirements. Instead of continuous operation, predrivers are enabled only when needed according to the driver layer configuration, creating a periodic activation pattern that maintains signal buffering capability when required while eliminating unnecessary power consumption during periods when fewer drivers are active.
Solution Approach 2:
The patent extracts and removes the unnecessary power consumption by selectively disabling predriver stages that are not needed for the current operational configuration. By taking out the inactive predrivers from the active circuit, the system maintains adequate signal buffering through only the necessary predriver stages, eliminating waste energy while preserving reliability.
Data Source
AI summary
A transmitter includes driver slices coupled to its output. Each driver slice includes a first differential predriver that is selectively enabled and disabled by a first switch based on a control code configuration. A second differential predriver provides a first differential buffered data signal to a first group of driver slices when the second differential predriver is enabled. A second switch enables the second differential predriver when the control code is configured to enable the first differential predriver in at least one driver slice in the first group of driver slices. A third differential predriver provides a second differential buffered data signal to a second group of driver slices when the third differential predriver is enabled. A third switch enables the third differential predriver when the control code is configured to enable the first differential predriver in at least one driver slice in the second group of driver slices.