Differential Programming Two-Terminal Memory Intrinsic Error Suppression
Solution Overview
Problem
Current resistive-switching memory technologies face challenges in differential programming of multiple two-terminal memory cells, leading to potential invalid data results and high power consumption due to the lack of efficient mechanisms for intrinsic suppression and disconnection of program cycles.
Innovation Solution
The proposed solution involves an architecture for differential programming of multiple two-terminal resistive switching memory cells, where a program cycle is applied to a bitline coupled to multiple memory cells, and the second terminals are electrically shorted using a wordline-activated switch, allowing intrinsic suppression of non-programmed cells and disconnection of the program cycle upon detecting a program event, thereby mitigating invalid data and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If differential programming is applied to multiple two-terminal memory cells without intrinsic suppression mechanism, then programming operation can be performed on multiple cells simultaneously, but invalid data results occur due to lack of control over program events
Solution Approach 1:
The patent implements a feedback mechanism where the sense amplifier continuously monitors the bitline voltage during programming operation. When a program event is detected (indicating a memory cell has transitioned to conductive state), the feedback signal triggers immediate disconnection of the bitline from the voltage source, preventing further uncontrolled programming and ensuring data accuracy while maintaining high productivity
2Productivity
If program cycle is applied to multiple memory cells without disconnection mechanism, then programming can be performed on all cells, but high power consumption occurs due to continuous voltage application
Solution Approach 1:
The patent implements periodic action by alternating between voltage application and disconnection phases. The bitline is connected to the voltage source during programming operations, then disconnected when program events are detected or the programming cycle is complete. This periodic connection-disconnection pattern significantly reduces average power consumption while maintaining high programming throughput through parallel operation on multiple cells
Solution Approach 2:
The feedback mechanism from the sense amplifier triggers immediate disconnection of the bitline when program events are detected, preventing continuous power consumption. This feedback-based power management ensures that voltage is applied only when necessary for programming operations, reducing overall power consumption while maintaining high productivity
Data Source
AI summary
Improved differential programming of multiple two-terminal memory cells that define an identifier bit is provided. A differential circuit can be defined by a plurality of resistive memory cells connected to a single bitline of an array, with respective wordlines coupling second terminals of the memory cells to ground (or low voltage). Some disclosed circuits can provide very rapid intrinsic suppression of a non-programmed memory cell(s) defining an identifier bit in response to programming of another memory cell (or group of cells) defining the identifier bit. Differential programming can reduce power consumption and mitigate or avoid invalid data results for an identifier bit.