Differential RC Calibration Circuit for Parasitic Error Cancellation
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Solution Overview
Problem
Existing RC time constant calibration methods in sigma-delta analog-to-digital converters face inaccuracies due to parasitic elements, especially at high clock frequencies, where small parasitic capacitances can lead to significant calibration errors, exceeding acceptable limits for high-performance applications.
Innovation Solution
A time constant calibration circuit with variable resistor and capacitor, utilizing a reference current source and comparator to iteratively adjust resistance and capacitance values through multiple calibration cycles, minimizing the impact of parasitic elements and achieving precise RC time constant calibration in a reduced number of phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional RC time constant calibration methods are used, then calibration can be performed, but parasitic capacitances cause significant inaccuracies (up to 10% error) especially at high clock frequencies
Solution Approach 1:
The patent extracts and eliminates the harmful effect of parasitic capacitances by using a differential measurement approach. The calibration circuit measures the difference between two RC time constants (one with parasitic capacitance, one without), thereby canceling out the parasitic effect. This is achieved by configuring the operational amplifier to compare voltages developed across capacitors C1 and C2, where the differential measurement removes the common-mode parasitic capacitance contribution.
Solution Approach 2:
The patent changes the measurement parameter from absolute time constant measurement to differential time constant measurement. By measuring the difference between two RC products (R1C1 - R2C2) rather than absolute values, the circuit achieves immunity to parasitic capacitances. The operational amplifier configuration enables this parameter transformation, allowing accurate calibration despite the presence of parasitic elements.
2Measurement precision
If multiple calibration cycles with iterative adjustment are implemented, then calibration precision is improved, but calibration time and complexity increase
Solution Approach 1:
The patent performs preliminary action by pre-configuring the calibration circuit with matched components (R1=R2, C1=C2) and predetermined switch states. The operational amplifier is pre-biased and the capacitors are pre-charged to known voltages before the actual measurement begins. This preliminary setup eliminates the need for complex iterative adjustments during calibration, reducing calibration time while maintaining high precision through the inherent differential measurement capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces calibration inaccuracies caused by parasitic capacitances and achieves precise RC time constant calibration, ensuring accurate operation of sigma-delta ADCs even at high clock frequencies, meeting the stringent accuracy requirements for high-performance applications.
Implementation Method 1
A capacitor C to be calibrated is connected to an operational amplifier configured as an integrator
Implementation Method 2
An operational amplifier configured as an integrator has a capacitor C connected between an inverting input and an output
Data Source
AI summary
A time constant calibration circuit and method. The circuit comprises a resistor, a capacitor, an amplifier, a first switch and a second switch. The resistance of the resistor and/or the capacitance of the capacitor is variable. A first terminal of the resistor, a first terminal of the capacitor and a first input of the amplifier are coupled to a common node, which is coupleable to a reference current source. A second input of the amplifier is coupleable to a reference voltage. An output of the amplifier is coupled to a second terminal of the resistor and a second terminal of the capacitor. The circuit can perform a calibration process comprising one or more calibration cycles in which the switches route a reference current through the resistor in a first phase and through the capacitor in a second phase. The resistance and/or the capacitance is adjusted between calibration cycles.