Differential Receiver Circuit with Constant Propagation Delay
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Solution Overview
Problem
Differential receivers in semiconductor integrated circuits face challenges such as high standby current consumption and varying propagation delays due to common mode bias, which are unacceptable for critical timing paths, especially at high frequencies.
Innovation Solution
A differential receiver circuit that consumes substantially no standby power and has constant propagation delay, utilizing first and second pass circuits and buffers to receive differential input signals, with cross-coupled inverters and final drive buffers to generate differential output signals while maintaining timing characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a differential receiver based on differential transistor pairs with constant current source is used, then common mode noise rejection is improved, but standby current consumption increases significantly
Solution Approach 1:
The patent implements a differential receiver that operates periodically rather than continuously. The receiver circuit is enabled only when differential signals need to be processed, and disabled (entering standby mode) when no signals are present. This periodic operation eliminates continuous standby current consumption while maintaining common mode noise rejection capability when active.
Solution Approach 2:
The patent employs dynamic control of the differential receiver circuit, transitioning between active and standby states based on signal presence. Control logic dynamically enables or disables the differential transistor pairs and constant current sources, making the system adaptive to operational requirements and eliminating unnecessary power consumption during idle periods.
2Reliability
If conventional differential receivers are used, then differential signal reception is achieved, but propagation delay varies due to common mode bias
Solution Approach 1:
The patent incorporates feedback mechanisms that monitor the common mode bias level and adjust the operating parameters of the differential receiver accordingly. This feedback control compensates for variations in propagation delay caused by common mode bias, maintaining consistent timing characteristics while preserving accurate differential signal reception.
Solution Approach 2:
The patent dynamically adjusts operating parameters such as current source levels and transistor biasing conditions based on detected common mode bias variations. By changing these parameters in response to common mode conditions, the receiver maintains constant propagation delay while continuing to accurately receive differential signals.
Data Source
AI summary
A differential receiver circuit on an integrated circuit consumes substantially no standby power, has constant propagation delay regardless of the input common mode bias, has acceptable common mode rejection and includes first and second pass circuits and buffers to receive differential input signals. The first pass circuit provides a true output signal based on a differential between the “true” buffered signal and the complimentary buffered signal. The second pass circuit provides a “complementary” output signal based on a differential between the complimentary buffered signal and the “true” buffered signal. The differential receiver circuit rejects common mode biases that may be present on the received differential signals without varying propagation delay times.