Differential Receiver Fail-Safe Switching for Glitch Suppression

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Solution Overview

Problem

Existing receiver circuitry in RS-485 transceivers experiences glitches due to noise propagation when transmitter circuitry is disabled, which is difficult to mitigate due to stringent specifications and variations in manufacturing, power supply voltage, and temperature.

Innovation Solution

Implementing a receiver circuit with switches and fail-safe circuitry that decouples the comparator from the attenuator during transmitter disablement, applying a fail-safe voltage to stabilize the comparator input, and re-coupling after a controlled isolation interval to prevent glitches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the transmitter circuitry is disabled, then power consumption is reduced and communication mode can be switched, but noise propagation causes glitches at the receiver output

Engineering Contradiction:
Improvepower consumptionVSAvoidsignal integrity
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

A fail-safe circuit is introduced as an intermediary between the attenuator and comparator. This circuit includes a fail-safe voltage generator that produces a stable reference voltage and a switch that couples or decouples this voltage from the comparator input based on transmitter state, thereby mediating the noise propagation issue while maintaining receiver reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The fail-safe circuit proactively generates a stable reference voltage and prepares the decoupling mechanism before noise propagation occurs. When the transmitter is disabled, the circuit preemptively decouples the comparator from the noisy attenuator output and couples it to the stable fail-safe voltage, preventing glitches before they can occur

Inventive Principle:
Principle #10Preliminary action

2Reliability

If switches are added to decouple the comparator from the attenuator, then glitch prevention is achieved, but device complexity increases

Engineering Contradiction:
Improveglitch preventionVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The fail-safe circuit merges multiple functions into a single integrated block: the fail-safe voltage generator, the decoupling switch, and the coupling control logic are combined in one circuit module. This consolidation achieves glitch prevention while minimizing the increase in overall device complexity by combining related functions rather than adding separate independent components

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The fail-safe circuit serves multiple functions simultaneously: it generates a stable reference voltage, decouples the comparator from noise during transmitter disablement, and provides a default stable state for the comparator input. This multi-functionality reduces the need for additional separate circuits, thereby limiting complexity increase

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If the comparator is decoupled during transmitter disablement, then noise propagation is prevented, but data transmission delay increases

Engineering Contradiction:
Improvenoise rejectionVSAvoiddata transmission delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The coupling state of the fail-safe circuit is dynamically adjusted based on the transmitter enable/disable state. The switch controlled by the transmitter enable signal continuously changes the circuit configuration: coupled to the attenuator output during transmission mode for normal operation, and decoupled during receiver mode to prevent noise. This dynamic adaptation prevents fixed delays while maintaining noise rejection when needed

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20260106605A1Glitch Reduction in High-Speed Differential Receivers
Publication Date: 2026.04.16 TEXAS INSTRUMENTS INC
  • US20260106605A1 patent drawing
  • US20260106605A1 patent drawing
  • US20260106605A1 patent drawing

AI summary

A differential transceiver including a driver circuit and a receiver circuit, and a serial communications network including the transceiver. The receiver circuit includes an input resistor attenuator, having first and second attenuator inputs coupled to the first and second terminals, respectively, a differential comparator having first and second comparator inputs, and an output buffer having an input coupled to the output of the comparator. The receiver circuit further includes a first switch coupling the first attenuator output to the first comparator input, a second switch coupling the second attenuator output to the second comparator input, and a fail-safe circuit including first and second current sources coupled to the first and second comparator inputs, respectively, and third and fourth switches coupled in series between the first and second current sources.