Differential Receiver Input Multiplexing to Cut Latency and Jitter
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Solution Overview
Problem
Existing high-speed interfaces for network components suffer from latency and jitter due to the use of parallel paths and multiplexers, which impair the data path and cause performance penalties.
Innovation Solution
A high-speed interface design that integrates a multiplexing function within the receiver's first stage, using a common path for both functional and wrap data, eliminating the need for a traditional multiplexer and enabling reduced latency and jitter by employing field effect transistors and a common operating point for signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional multiplexer is used in the data path to implement wrap path, then functionality verification is enabled, but latency and jitter are increased in the data signal
Solution Approach 1:
The patent merges the functional data path and wrap data path into a single integrated receiver structure. Both data types share common components including the differential receiver, decision circuit, and output buffer, eliminating the need for separate multiplexer switching. This consolidation allows the system to maintain functionality verification capabilities while removing the latency and jitter introduced by traditional multiplexer-based wrap path implementation.
Solution Approach 2:
The receiver circuit is designed to handle both functional data and wrap data through a universal data path. The decision circuit selectively processes either functional or wrap data based on control signals, allowing the same hardware infrastructure to serve multiple purposes without requiring dedicated multiplexer stages for each data type.
2Reliability
If a mirror wrap path is created separate from the functional data path, then functionality verification is achieved, but the actual data path circuitry is not utilized and performance penalty occurs
Solution Approach 1:
The patent consolidates the functional data path and wrap data path into a single shared infrastructure. The same differential receiver, decision circuit, and output buffer handle both data types, ensuring that the actual data path circuitry is fully utilized for both functional operations and wrap-around verification, thereby eliminating performance penalties associated with separate mirror paths.
3Adaptability or versatility
If a multiplexer is placed in the data path to enable wrap path multiplexing, then wrap functionality is enabled, but added latency and jitter are introduced
Solution Approach 1:
The patent extracts the multiplexer component from the data path entirely. Instead of using a multiplexer to switch between functional and wrap data, the system employs a unified receiver structure with a decision circuit that selectively processes the appropriate data type. This removal of the multiplexer eliminates the source of latency and jitter, maintaining signal stability while preserving wrap path capability.
Data Source
AI summary
A design structure embodied in a machine readable medium used in a design process includes high-speed interface between a first network component and a second network component, the interface including a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP) coupled to a negative output circuit (OUTN) and the negative voltage input (VINN) by a positive input bus and a negative input bus, the negative voltage input (VINN) also coupled to a positive output circuit (OUTP). Implementing the high-speed interface calls for applying a bias to the a positive input bus and a negative input bus to periodically multiplex a data signal, thus providing a common receiving path for functional data and wrap data of the data signal.