Differential Signal Receiver Circuit for Spurious Pulse Rejection
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Solution Overview
Problem
Conventional isolated gate driver devices suffer from spurious pulses in the reconstructed signal due to common-mode ringing effects, which are not effectively addressed by existing solutions that require costly and area-consuming implementations of isolation capacitors in the high-voltage die.
Innovation Solution
A receiver circuit with a logic circuit that corrects spurious pulses by detecting and discarding pulses exceeding a certain duration threshold, using asymmetric buffers and gating logic gates to produce corrected set and reset signals, improving common-mode transient immunity without additional hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation capacitors are implemented in the high-voltage die to address common-mode ringing effects, then common-mode transient immunity is improved, but device area and manufacturing cost increase
Solution Approach 1:
The patent extracts the isolation capacitor implementation from the high-voltage die and relocates it to the low-voltage die. This removes the problematic element (isolation capacitors in high-voltage die) that causes area consumption and manufacturing complexity while preserving the essential galvanic isolation function through alternative means.
Solution Approach 2:
The patent introduces a receiver circuit with pulse detection and correction logic as an intermediary mechanism. This receiver circuit detects spurious pulses generated by common-mode ringing and corrects them through logic circuits, thereby improving common-mode transient immunity without requiring physical isolation capacitors in the high-voltage die.
2Reliability
If isolation capacitors are implemented in the high-voltage die to address common-mode ringing effects, then common-mode transient immunity is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the isolation capacitor implementation from the high-voltage die and relocates it to the low-voltage die. This removes the problematic element (isolation capacitors in high-voltage die) that causes manufacturing complexity while preserving the essential galvanic isolation function through alternative means.
Solution Approach 2:
The patent substitutes the physical hardware solution (isolation capacitors in high-voltage die) with a logical/software-based solution (receiver circuit with pulse detection and correction logic). This replaces the mechanical/electrical implementation with a signal processing approach, thereby reducing manufacturing complexity and cost.
3Device complexity
If conventional receiver circuits are used without pulse correction logic, then device complexity is reduced, but spurious pulses cause incorrect output signal transitions
Solution Approach 1:
The patent implements a feedback mechanism in the receiver circuit where the output signal is fed back to the pulse detection logic. The detection logic monitors both the differential input signal and the output signal, and when a spurious pulse is detected (by comparing expected vs. actual output transitions), correction logic is activated to prevent incorrect output transitions.
Solution Approach 2:
The patent introduces an intermediary detection and correction logic circuit between the differential input signal and the output signal. This intermediary layer analyzes the incoming differential signal, detects spurious pulses, and controls the output signal generation accordingly, thereby ensuring signal decoding accuracy without significantly increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed receiver circuit effectively reduces spurious pulses, ensuring robust signal decoding and minimizing incorrect output signal transitions, thus enhancing the reliability of isolated gate driver devices.
Implementation Method 1
A first comparator circuit is configured to convert the differential signal into an intermediate set signal including a pulse at each spike of the differential signal having the first polarity
Implementation Method 2
A second comparator circuit is configured to convert the differential signal into an intermediate reset signal including a pulse at each spike of the differential signal having the second polarity
Data Source
AI summary
A receiver circuit receives a differential signal that includes positive and negative spikes, and produces an output signal as a function of the differential signal. A first comparator produces an intermediate set signal that includes a pulse at each positive spike of the differential signal, and a second comparator produces an intermediate reset signal that includes a pulse at each negative spike of the differential signal. A logic circuit detects whether the digital signal switches between a first value and a second value, and whether the intermediate reset signal and the intermediate set signal include pulses lasting longer than a threshold. The logic produces a set correction signal and a reset correction signal. The logic circuit produces a corrected set signal and a corrected reset signal. An output circuit produces an output signal based on the corrected set signal and the corrected reset signal.