Differential Reception Circuit for Low-Voltage Clock Stability

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Solution Overview

Problem

Existing electronic devices face challenges in efficiently amplifying and stabilizing voltage differences between input signals of varying voltages, which affects the generation of internal clocks and data processing operations.

Innovation Solution

The electronic device incorporates a reception circuit with PMOS and NMOS transistors, capacitors, and a current source to amplify voltage differences between input and inverted input signals, generating an internal clock and stabilizing its frequency, even when input signals have low voltages, thereby maximizing voltage ranges and reducing current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a differential amplification circuit is used to amplify voltage differences, then the voltage range is maximized and current consumption is reduced, but the circuit becomes complex and difficult to stabilize

Engineering Contradiction:
Improvecurrent consumptionVSAvoidcircuit complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The reception circuit is divided into multiple functional blocks: an input unit for receiving differential signals, a current source for generating bias currents, and an output unit for driving the output node. This segmentation allows each block to be optimized independently, reducing overall circuit complexity while maintaining low current consumption

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A capacitor is introduced as an intermediary element connected to the output node. This capacitor stabilizes the output voltage and helps maintain signal integrity without requiring additional active components, thus reducing circuit complexity while preserving energy efficiency

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the reception circuit directly receives power supply voltage and ground voltage, then the voltage range is maximized, but the circuit becomes sensitive to voltage fluctuations and harder to control

Engineering Contradiction:
Improvevoltage rangeVSAvoidvoltage stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The current source is configured to generate bias currents that automatically adjust in response to voltage fluctuations at the power supply and ground terminals. This feedback mechanism stabilizes the differential voltage at the output node, maintaining reliability while preserving the full voltage range

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The circuit uses controlled changes in current parameters through the current source to compensate for voltage variations. By dynamically adjusting the bias current based on voltage conditions, the circuit maintains stable operation across the full voltage range without sacrificing reliability

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If PMOS and NMOS transistors are used in the current source, then current control precision is improved, but the device complexity increases

Engineering Contradiction:
Improvecurrent control precisionVSAvoidtransistor configuration
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The PMOS and NMOS transistors are merged into a single current source block that generates both pull-up and pull-down currents. This combining approach achieves precise current control through coordinated transistor operation while avoiding the complexity of separate current control circuits

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250015771A1Electronic devices and electronic systems
Publication Date: 2025.01.09 SK HYNIX INC
  • US20250015771A1 patent drawing
  • US20250015771A1 patent drawing
  • US20250015771A1 patent drawing

AI summary

An electronic device includes a capacitor connected to an output node of a reception circuit. The reception circuit includes an input unit receiving an input signal and an inverted input signal. The reception circuit also includes a current source including a first PMOS transistor positioned between a power supply voltage terminal and a first internal node and a first NMOS transistor positioned between a ground voltage terminal and a second internal node, the current source configured to amplify a voltage difference of the input signal and the inverted input signal. The reception circuit further includes an output unit driving the output node according to a current supplied from the current source.