Differential Sample-and-Hold Circuit for Small-Area Accurate DACs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital-to-analog converter circuits for liquid crystal displays face challenges in reducing circuit area while maintaining high accuracy, particularly due to input capacitance effects from amplifier gate capacitance, which leads to output errors when capacitance values are minimized for area savings.
Innovation Solution
A sample and hold circuit with first and second capacitance elements connected via switches, and a differential circuit with a differential input stage and amplifier stage, where the switches control sampling and charge redistribution to minimize output errors from input capacitance, allowing for reduced capacitance values and smaller circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If capacitance values are minimized to reduce circuit area, then circuit area is reduced, but output errors increase due to input capacitance effects from amplifier gate capacitance
Solution Approach 1:
The patent divides the single capacitance function into two separate capacitance elements (first and second capacitance elements). This segmentation allows independent optimization of each element's value and characteristics, enabling reduced total capacitance while maintaining accurate charge distribution for DAC output precision.
Solution Approach 2:
The patent introduces a differential circuit as an intermediary between the capacitance elements and the output amplifier. This differential circuit compensates for input capacitance effects from the amplifier gate capacitance, allowing smaller capacitance values without sacrificing output accuracy.
2Area of stationary object
If capacitance values are reduced for area savings, then circuit area decreases, but charge distribution accuracy deteriorates
Solution Approach 1:
By separating the capacitance function into two elements connected through a differential circuit, each element can be optimized for minimal area while the differential circuit ensures accurate charge distribution by compensating for amplifier input capacitance effects.
Solution Approach 2:
The patent changes the operational parameters by using a differential circuit configuration that actively compensates for capacitance effects. This allows the system to operate with smaller capacitance values while maintaining precision through parameter optimization in the differential stage.
3Area of stationary object
If circuit area is minimized, then device integration is improved, but output voltage accuracy decreases due to amplifier gate capacitance effects
Solution Approach 1:
The differential circuit serves as an intermediary that isolates the capacitance elements from the amplifier's input capacitance effects. This mediation allows the use of smaller capacitance values for area reduction while the differential stage compensates for accuracy losses.
Solution Approach 2:
The differential circuit implements a form of feedback by continuously monitoring and compensating for voltage differences caused by amplifier gate capacitance. This feedback mechanism maintains output voltage accuracy even when capacitance values are minimized for area savings.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures highly accurate output voltages with reduced capacitance values, effectively minimizing output errors and allowing for area savings in digital-to-analog converter circuits used in liquid crystal display data drivers.
Implementation Method 1
first and second capacitance elements having one ends connected via a first switch
Data Source
AI summary
Disclosed is a sample and hold circuit including a differential circuit, an amplifier stage and a sampling voltage supply circuit. The differential circuit includes first and second capacitance elements, electric charge of which is distributed by a first switch, a first MOS transistor having a gate connected via a second switch to one end of the first capacitance element and also connected via a third switch to an output terminal, and having a source connected to a first current source, a second MOS transistor having a gate connected to one end of the second capacitance element and having a source connected to a second current source and also connected via a forth switch to the source of the first MOS transistor, and a load circuit connected between the drains of the first and second MOS transistors and a terminal of a second power supply. The amplifier stage receives an output of the differential circuit and has an output connected to the output terminal. The sampling voltage supply circuit delivers a sampling voltage to the one end of at least one of the first and second capacitance elements.