Differential Sampling Circuit for Switch Distortion Cancellation

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Solution Overview

Problem

Sample and hold circuits suffer from distortion due to the varying drain-source resistance of transmission gate switches, which affects the total harmonic distortion performance and introduces non-linear parasitic capacitances, leading to secondary distortion mechanisms.

Innovation Solution

A sampling circuit with dissimilar capacitors and switches is designed, where the errors in each channel are estimated and processed to cancel each other out, using a combination of NMOS and PMOS transistors in parallel and series configurations to compensate for switch resistances and parasitic capacitances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the on resistance of the FETs is reduced by making the transistors wider, then the switch resistance decreases, but the parasitic capacitances increase causing secondary distortion

Engineering Contradiction:
Improveswitch resistanceVSAvoidparasitic capacitance distortion
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The sampling circuit is divided into two separate signal paths, each with its own sampling capacitor and switch. By segmenting the circuit and using dissimilar components in each path, the patent creates differential error cancellation where the distortion effects in one path compensate for the other path's distortions, resolving the contradiction between low resistance and low parasitic capacitance requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent deliberately uses dissimilar capacitors and switches in the two signal paths, creating asymmetric component values. This asymmetry ensures that the sampling errors and distortion effects differ between paths, enabling error cancellation when the differential output is formed, thus reducing overall distortion without requiring perfectly optimized individual components.

Inventive Principle:
Principle #4Asymmetry

2Ease of operation

If transmission gate switches are used in sample and hold circuits, then the switching performance improves, but the varying drain-source resistance with input voltage causes distortion

Engineering Contradiction:
Improveswitching performanceVSAvoidtotal harmonic distortion
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The patent implements a feedback mechanism where the output of one signal path is compared with the other path's output. The differential amplifier continuously monitors both paths and the varying resistance effects are canceled through this feedback comparison, allowing transmission gates to be used for their superior switching performance while maintaining low distortion through active error cancellation.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the parameters of the two signal paths by using dissimilar capacitor values and switch configurations. This parameter differentiation ensures that the voltage-dependent resistance variations affect each path differently, and when the differential output is formed, these parameter differences cause the distortion components to cancel each other out.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8816887B2Sampling circuit, a method of reducing distortion in a sampling circuit, and an analog to digital converter including such a sampling circuit
Publication Date: 2014.08.26 ANALOG DEVICES INC
  • US8816887B2 patent drawing
  • US8816887B2 patent drawing
  • US8816887B2 patent drawing

AI summary

A sampling circuit comprising: an input node; a first signal path comprising a first sampling capacitor and a first signal path switch in a signal path between the input node and a first plate of the first sampling capacitor; a second signal path comprising a second sampling capacitor and a second signal path switch in a signal path between the input node and a first plate of the second sampling capacitor, and a signal processing circuit for forming a difference between a signal sampled onto the first sampling capacitor and a signal sampled onto the second sampling capacitor.