Differential Sampling Circuit With Extended Hold Time
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Solution Overview
Problem
Existing sampling circuits face challenges in achieving high sampling speed and long hold-time while maintaining low hardware effort, leading to sub-optimal performance in analog-digital conversion systems.
Innovation Solution
The proposed sampling device incorporates a voltage-current-converter, sampling transistors, demultiplexing circuits, and a dump circuit to efficiently convert and hold differential signals, allowing for high-speed sampling and extended hold-times with minimal hardware resources. This is achieved through the use of current-source transistors, demultiplexing transistors, and a clock signal generator that doubles hold-time without significant additional hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sampling circuits are used, then the circuit structure is simple, but the sampling speed is sub-optimal
Solution Approach 1:
The sampling circuit is divided into multiple independent parallel paths, each handling a portion of the sampling task. This segmentation allows each path to operate at high speed while the overall system maintains manageable complexity through modular organization.
Solution Approach 2:
The patent transitions from single-ended to differential signaling, adding a dimensional aspect to the signal processing. This differential approach enables higher sampling speeds by providing balanced signal paths that reduce interference and improve signal integrity.
2Duration of action of moving object
If conventional sampling circuits are used, then the hardware effort is low, but the hold-time is insufficient
Solution Approach 1:
The circuit performs preliminary charging of the holding capacitor during the sampling phase, preparing the signal for extended holding. This preliminary action ensures that the capacitor is fully charged to the correct voltage level before the holding phase begins, enabling longer hold-times without additional hardware.
Solution Approach 2:
The sampling transistors serve multiple functions: they act as switches for sampling, as charge pumps for capacitor charging, and as part of the holding mechanism. This multi-functionality extends hold-time without requiring separate dedicated components for each function.
3Measurement precision
If conventional sampling circuits are used, then the circuit is simple, but the sampling accuracy is sub-optimal
Solution Approach 1:
Instead of sampling the voltage directly and then converting, the patent inverts the approach by sampling the differential current and then converting to voltage. This inversion improves sampling accuracy by reducing the impact of parasitic capacitances and improving the signal-to-noise ratio during the critical sampling instant.
Solution Approach 2:
The patent introduces an intermediate current stage between the input signal and the final output. This intermediary current mode operation allows for more accurate signal representation and reduces errors that would otherwise occur in direct voltage sampling, thereby improving measurement precision.
4Speed
If high sampling speed is achieved, then the bandwidth is improved, but the linearity may deteriorate
Solution Approach 1:
The patent applies different optimization strategies to different parts of the circuit: the sampling transistors are optimized for high-speed operation with appropriate sizing and positioning, while the holding capacitors and reset circuits are optimized for linearity and stability. This local quality approach allows each component to perform its specific function optimally without compromising overall linearity.
Data Source
AI summary
A sampling device (50) serves the purpose of sampling a differential measuring voltage. The sampling device (50) comprises at least a first holding device (52), a second holding device (53) and a multiplexing circuit (54), which is adapted to provide a differential sample of a sampled differential signal, derived from the differential measuring voltage by sampling with a first clock signal of a first clock rate, to the first holding device (52), at the occurrence of each HIGH-value of a second clock signal of a second clock rate being half of the first clock rate and provide a differential sample of the sample differential signal to the second holding device (53), at the occurrence of each LOW-value of the second clock signal. Furthermore, the sampling device (50) comprises a reset device (51), adapted to reset the second holding device (53) at or after the occurrence of each HIGH-value of the second clock signal and reset the first holding device (52) at or after the occurrence of each low value of the second clock signal.