Differential SAR ADC Layout With Quantization Error Hold Circuits
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Solution Overview
Problem
Successive approximation type A/D converter circuits face challenges in increasing accuracy and signal-to-noise ratio, particularly when compared to delta sigma type converters, and lack efficient layout configurations for differential configurations.
Innovation Solution
A circuit device incorporating a charge redistribution type D/A converter and quantization error hold circuits, with capacitor array circuits and quantization error hold circuits placed along a first direction and connected with short wiring, allowing for a differential configuration that includes a comparator and adder circuit to perform noise shaping and multichannel input capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a successive approximation type A/D converter circuit is used, then power consumption is low, but accuracy (number of valid bits) cannot be increased
Solution Approach 1:
The A/D converter is divided into two functional segments: a successive approximation type A/D converter for basic conversion and a delta sigma type A/D converter for accuracy enhancement. The successive approximation converter handles the primary conversion with low power consumption, while the delta sigma converter processes the residual error signal to increase the number of valid bits, thereby achieving high accuracy without significantly increasing overall power consumption.
Solution Approach 2:
The invention changes the operational parameters by introducing oversampling and noise shaping mechanisms. The delta sigma converter oversamples the input signal and shapes the quantization noise spectrum, pushing noise to higher frequencies where it can be filtered out. This parameter change enables the system to achieve higher effective resolution without proportionally increasing power consumption.
2Measurement precision
If a differential configuration is adopted to improve accuracy and S/N ratio, then measurement precision improves, but device complexity increases
Solution Approach 1:
The layout employs asymmetric placement strategies to optimize the differential configuration. The capacitor arrays for the positive and negative differential sides are placed in different orientations (one horizontal, one vertical) to minimize parasitic coupling while maintaining differential symmetry in function. This asymmetric physical layout reduces interference and improves S/N ratio without requiring a fully symmetric complex structure.
Solution Approach 2:
The invention utilizes spatial dimensionality by placing the positive and negative capacitor arrays in orthogonal directions (one along the first direction, the other along the second direction). This dimensional separation reduces parasitic coupling between differential signals while maintaining electrical symmetry, thereby improving S/N ratio without proportionally increasing circuit footprint or complexity.
3Ease of manufacture
If capacitor arrays are placed along the first direction and quantization error hold circuits are placed along the second direction, then layout efficiency improves and wiring length is reduced, but area of stationary object increases
Solution Approach 1:
The layout transitions from a planar arrangement to a two-dimensional orthogonal configuration. Capacitor arrays are placed along the first direction while quantization error hold circuits are placed along the second direction, utilizing both spatial dimensions efficiently. This orthogonal arrangement reduces the total area required compared to a linear layout, as it better utilizes the available chip real estate in both directions.
Solution Approach 2:
The layout is pre-optimized by placing quantization error hold circuits adjacent to their corresponding capacitor arrays in the orthogonal direction. This preliminary spatial arrangement minimizes the wiring length required to connect these components before routing, reducing parasitic effects and simplifying the routing process, thereby improving manufacturability without excessive area consumption.
Data Source
AI summary
A circuit device includes an A/D converter circuit that performs A/D conversion by successive approximation using a charge redistribution type D/A converter circuit having capacitor array circuits on the positive electrode side and the negative electrode side, and quantization error hold circuits that hold charges corresponding to a quantization error in the A/D conversion. The quantization error hold circuits include quantization error hold circuits on the positive electrode side and the negative electrode side having one ends connected to sampling nodes of the capacitor array circuits on the positive electrode side and the negative electrode side. The quantization error hold circuits on the positive electrode side and the negative electrode side are placed on a second direction side orthogonal to a first direction in which the capacitor array circuits on the positive electrode side and the negative electrode side are placed.