Differential SAR ADC Reference Switching for Lower Power Conversion
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Solution Overview
Problem
Analog-to-digital converters (ADCs) consume a significant portion of power in electronic devices, particularly due to the high power consumption associated with comparing input signals to reference signals, which is not efficiently reduced despite advancements in semiconductor technology.
Innovation Solution
The proposed ADC design employs a comparator with two digital-to-analog converters (DACs) and capacitor banks, using signed binary values to minimize the switching of capacitors, especially for sparse signals, by adjusting digital reference signals to approximate the difference between input signals, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a Flash-ADC is used to achieve fast conversion speed, then the conversion speed is improved, but the power consumption increases significantly
Solution Approach 1:
The patent divides the conversion process into multiple sequential stages (successive approximation steps) rather than performing all comparisons simultaneously. The SAR ADC performs bit-by-bit conversion from most significant bit to least significant bit, segmenting the single high-power Flash-ADC operation into multiple lower-power steps, thereby reducing overall power consumption while maintaining acceptable conversion speed.
Solution Approach 2:
The patent employs periodic switching of capacitors in the DAC during the successive approximation process. Capacitors are switched in a systematic sequence corresponding to each bit determination, allowing the system to perform conversions in periodic cycles rather than continuous high-power operation, thus reducing average power consumption.
2Use of energy by moving object
If the number of capacitor switches is reduced to decrease power consumption, then the power efficiency is improved, but the conversion precision may be affected
Solution Approach 1:
The patent performs preliminary comparisons starting from the most significant bit before proceeding to less significant bits. By determining the MSB first and progressively refining the result, the system achieves high precision without requiring all capacitors to switch simultaneously or repeatedly, thereby maintaining conversion accuracy while reducing overall switching activity and power consumption.
Solution Approach 2:
The patent dynamically adjusts the switching behavior of capacitors based on the progression of the conversion process. As each bit is determined through comparison, the capacitor switching pattern adapts to reflect only the necessary adjustments, optimizing the balance between precision requirements and power consumption by avoiding unnecessary switching operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces power usage by minimizing capacitor switching, especially for sparse signals, leading to more efficient ADC operation and lower overall power consumption in electronic devices.
Implementation Method 1
The first DAC comprises a first capacitor bank having N number of first capacitors, wherein first plates of the first capacitors of the N number of first capacitors are controlled by bits of a first digital reference signal
Data Source
Figure 1~2
Figure 3
AI summary
An analog-to-digital converter, ADC, (1) is provided. The ADC comprises a comparator (2) having a first input and a second input. The ADC further comprises a first digital-to-analog converter, DAC, (3) and a second DAC (4) configured to receive a first and a second digital reference signal, respectively. The digital reference signals (Dref) represent a signed binary value. The ADC is configured to compare input voltages (Vin), based on a first sampled input signal of a differential input signal and the first digital reference signal, and based on a second sampled input signal of the differential input signal and the second digital reference signal and, based on said comparison, adjust the reference voltage so as to approximate the differential input signal.