Differential Sense Amplifier for Memory Cell Error Compensation
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Solution Overview
Problem
Existing split gate non-volatile memory cell arrays cannot individually correct over-programmed memory cells without erasing the entire row or array, requiring a new method to compensate for programming errors without affecting surrounding cells.
Innovation Solution
The introduction of a differential sense amplifier configuration that pairs memory cells as 'supercells' where the read outputs are connected to generate an output signal based on the difference in signal amplitudes, allowing for individual compensation of over-programmed cells by adjusting the programming of the paired cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional memory cell arrays are used with individual programming, then programming flexibility is improved, but the ability to correct over-programmed cells is worsened because the entire row or array must be erased
Solution Approach 1:
The memory array is segmented into pairs of memory cells called supercells, where each supercell consists of two memory cells that share common bit lines. This segmentation allows differential reading between paired cells, enabling correction of over-programming errors in individual cells without erasing the entire row or array.
Solution Approach 2:
The system implements feedback through differential sensing of paired memory cells. By comparing the read outputs of two memory cells in a supercell, the system can detect over-programming conditions and adjust subsequent programming operations accordingly, correcting errors without full array erasure.
2Manufacturing precision
If differential sense amplifier configuration is introduced, then programming accuracy is improved through error compensation, but device complexity increases
Solution Approach 1:
The sense amplifier system is segmented into multiple differential sense amplifiers, each handling a pair of memory cells (supercell). This segmentation distributes the sensing complexity across multiple simple differential amplifiers rather than requiring one complex amplifier for the entire array, making the increased complexity manageable and scalable.
Solution Approach 2:
The patent merges the sensing functions for two memory cells into a single differential sense amplifier operation. By combining the read outputs of paired memory cells into a differential signal, the system achieves error compensation while using relatively simple differential amplifier circuitry that can be replicated across the array.
3Manufacturing precision
If supercell pairing is implemented, then individual cell compensation is improved, but loss of time increases due to additional read operations
Solution Approach 1:
The system performs preliminary differential reads of supercell pairs during the programming process to detect over-programming conditions before finalizing the programming operation. This preliminary detection allows for immediate correction or adjustment, preventing the need for complete array erasure and re-programming, thus reducing overall time loss.
Solution Approach 2:
When over-programming is detected in a supercell, the system can skip the time-consuming full array erasure step and proceed directly to targeted correction of the affected cell. This rushing through of unnecessary steps (full erasure) significantly reduces the time penalty associated with error correction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise programming of memory cells by compensating for over-programming errors within the paired supercells without erasing surrounding cells, improving programming accuracy and efficiency.
Implementation Method 1
A differential amplifier amplifies a difference between signals outputted to the pair of these bit lines and outputs it to an I/O line
Implementation Method 2
The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the control gate 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation 24 from the floating gate 20 to the control gate 22 via Fowler-Nordheim tunneling
Implementation Method 3
The memory cell is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the control gate 22, and a positive voltage on the drain 16. Electron current will flow from the source 14 towards the drain 16. The electrons will accelerate and become heated when they reach the gap between the control gate 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide 26 onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20.
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output. For each of the differential sense amplifiers, the differential sense amplifier is configured to generate an output signal on the output having an amplitude that is based upon a difference in signal amplitudes on the first and second inputs, the first input is connected to one of the bit lines, and the second input is connected to another one of the bit lines. Alternately, one or more sense amplifiers are configured to detect signal amplitudes on the bit lines, and the device includes calculation circuitry configured to produce output signals each based upon a difference in signal amplitudes on two of the bit lines.