Differential Sensing Circuit Doubles Read Margin in Non-Volatile Memory
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Solution Overview
Problem
Conventional non-volatile memory (NVM) architectures, such as those using floating-gate and SONOS structures, face limitations including long program and erase times, high voltage requirements, complex fabrication processes, and issues with read disturb due to charge leakage, which result in limited read margin and incorrect data reads.
Innovation Solution
A differential sensing circuit and method that employs two reference cells, an erase reference cell and a program reference cell, coupled with current-to-voltage converters and a comparator, to generate an enhanced read margin output by mirroring currents and comparing voltage components, thereby doubling the read margin without the need for additional memory cells or complex adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-ended sensing configuration is used, then the circuit complexity is low, but the read margin is limited and incorrect data reads occur
Solution Approach 1:
The sensing circuit is segmented into multiple independent stacks: a first stack with a program reference cell, a second stack with an erase reference cell, and a third stack with a matrix cell. Each stack operates independently with its own current-to-voltage converter, allowing parallel processing of reference and data readings without interference, thereby improving read margin while maintaining manageable circuit complexity through modular architecture
Solution Approach 2:
Different reference cells are provided for different reading operations: a program reference cell specifically for program cell readings and an erase reference cell specifically for erase cell readings. This local specialization ensures that each reference cell is optimized for its specific function, improving the accuracy and read margin for each operation type while avoiding the need for a single imperfect universal reference
2Reliability
If floating-gate bit cells are used, then charge injection capability is achieved, but program and erase times are long and high voltages are required
Solution Approach 1:
The patent changes the fundamental operating parameters by using SONOS cells instead of floating-gate cells, enabling charge injection at lower voltages and faster times. The SONOS structure allows electron tunneling through a thin oxide layer at reduced voltage levels, dramatically decreasing program and erase times while maintaining charge retention capability
Solution Approach 2:
The patent replaces the floating-gate charge storage mechanism with a SONOS (Silicon-Oxygen-Nitrogen-Oxygen-Silicon) tunnel oxide-based charge storage mechanism. This substitution enables charge injection through a different physical process (electron tunneling through thin oxide) that occurs at lower voltages and faster rates compared to the floating-gate hot carrier injection process
3Reliability
If floating-gate structure is used, then charge storage capability is achieved, but fabrication process complexity increases
Solution Approach 1:
The patent adopts SONOS cells that can be fabricated using simpler, more cost-effective processes compared to floating-gate cells. The SONOS structure eliminates the need for complex floating-gate formation steps and requires fewer process stages, making the manufacturing process more economical and scalable while maintaining adequate charge storage capability for the application
4Ease of manufacture
If SONOS memories are used, then fabrication simplicity and scalability are improved, but charge leakage during read operations occurs
Solution Approach 1:
The patent introduces reference cells as intermediary elements that enable accurate reading without directly probing the matrix cells during read operations. By using reference cells to establish baseline current levels and comparing them with matrix cell currents through differential measurement, the system can detect charge states without causing charge leakage or disturbance to the stored data in the matrix cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively doubles the read margin in non-volatile memories by closely matching the characteristics of reference cells with matrix cells, reducing process and geometric mismatches, and eliminating the need for a reference current, thus improving data retention and endurance while minimizing area requirements.
Implementation Method 1
A differential sensing circuit includes a first current-to-voltage converter. The circuit includes a first current subtraction circuit having an erase reference cell
Implementation Method 2
Outputs of the first and second current-to-voltage converters are compared to generated an enhanced read margin output
Data Source
AI summary
A differential sensing circuit and method for enhancing read margin of a memory device are disclosed. The differential sensing circuit includes a first current-to-voltage converter. The circuit includes a first current subtraction circuit having an erase reference cell. A first input terminal of the first current-to-voltage converter is coupled to the first current subtraction circuit. The circuit includes a second current-to-voltage converter. The circuit also includes a second current subtraction circuit having a program reference cell. A first input terminal of the second current-to-voltage converter is coupled to the second current subtraction circuit. Both the first and second current subtraction circuits are coupled to a memory access bias signal. Outputs of the first and second current-to-voltage converters are compared to generate an enhanced read margin output.