Differential Signal Detection Circuit for Noise-Resistant Wake-Up
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Solution Overview
Problem
Conventional signal detection circuits in high-speed signal transmission systems are unable to accurately distinguish between real signals and noise, leading to potential missed data transmissions due to power consumption issues and complexity in maintaining both accuracy and simplicity.
Innovation Solution
A detecting circuit comprising a first offset generating circuit and a first sampling circuit, which applies an offset to an input signal pair to generate a differential output signal pair, allowing the sampling circuit to identify data signals by detecting voltage differences, thereby reducing false activations and improving detection precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional signal detection circuits are used in high-speed signal transmission systems, then the receiver can be awoken from sleep mode, but the circuit cannot accurately distinguish between real signals and noise, leading to detection inaccuracies
Solution Approach 1:
The patent segments the signal detection process into multiple stages: initial signal detection during sleep mode, followed by validation through sampling and comparison operations. The detection circuit is divided into functional blocks including offset generating circuits, sampling circuits, and comparison circuits that work sequentially to verify signal authenticity before awakening the receiver
Solution Approach 2:
The patent performs preliminary signal validation actions before the receiver fully awakens. The detection circuit samples the differential signal, compares it against threshold levels, and validates signal characteristics in advance to determine whether the receiver should be awakened, preventing premature or erroneous wake events
2Measurement precision
If complex signal detection circuits using analog peak-bottom holders are developed to improve detection accuracy, then signal detection precision improves, but power consumption increases with large level variation
Solution Approach 1:
The patent extracts and removes the complex analog peak-bottom holder circuits from the detection system. Instead, it employs simplified digital sampling circuits and comparison logic that achieve adequate detection precision without the excessive power consumption and circuit complexity of analog peak-holding mechanisms
Solution Approach 2:
The patent uses simple, low-power sampling and comparison operations that can be quickly performed and discarded, replacing complex analog circuits with inexpensive digital logic operations that consume minimal power while achieving the necessary detection accuracy
3Use of energy by moving object
If the receiver enters sleep mode to reduce current consumption, then power efficiency improves, but the receiver may miss inputted signals if it does not awake promptly
Solution Approach 1:
The patent performs preliminary signal detection and validation in the sleep mode before the receiver is awakened. The detection circuit continuously monitors for signal presence and validates detected signals through sampling and comparison, ensuring that the receiver is awakened only when a genuine signal is confirmed, thus maintaining both power efficiency and reception reliability
Solution Approach 2:
The patent implements a feedback mechanism where the detection circuit continuously monitors the differential signal and provides feedback about signal presence and validity. This feedback controls the wake-up decision, allowing the receiver to remain in sleep mode during noise conditions and awaken promptly when real signals are detected, balancing power consumption with signal reception reliability
Data Source
AI summary
A detecting circuit includes: a first offset generating circuit arranged to apply a first offset to an input signal pair comprising a positive input signal and a negative input signal and accordingly generate a first output signal pair comprising a first positive output signal and a first negative output signal; and a first sampling circuit coupled to the first offset generating circuit, the first sampling circuit arranged to sample a difference in voltage between the first positive output signal and the first negative output signal to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair.