Differential Speed Processors for Software Interaction Defect Detection

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Solution Overview

Problem

Identifying software interaction defects, such as race conditions, is challenging due to their dependency on precise system states, making them difficult to discover and reproduce, especially since testers often lack the deep internal program knowledge required to set up the necessary conditions using breakpoints.

Innovation Solution

The method involves executing testcases on processors operating at different speeds, either physically or effectively adjusted through no-op instructions, to increase the likelihood of detecting interaction defects by comparing results from singly and simultaneously run testcases, and generating an error notification when discrepancies are found.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If breakpoints are used to create precise system state, then interaction defects can be detected, but tester knowledge requirements and test complexity increase significantly

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidtest complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary mechanism (differential speed processing layer) between the test execution and the defect detection. This intermediary automatically manipulates processor speeds to create varying execution sequences, eliminating the need for testers to manually set breakpoints and understand internal program states. The intermediary handles the complexity of state manipulation while providing simple defect detection outputs.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If multiple testcases are executed simultaneously at different speeds, then interaction defects are more likely to be detected, but execution control and result comparison complexity increase

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidexecution control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making processor speeds variable rather than fixed. Different processors operate at different speeds during simultaneous testcase execution, creating dynamic variations in execution sequences. This dynamic speed variation automatically exposes race conditions and interaction defects without requiring complex static test setup. The system dynamically adjusts execution parameters to reveal defects that would be invisible under fixed-speed execution.

Inventive Principle:
Principle #15Dynamics

3Reliability

If precise system state is required to reproduce interaction defects, then defects can be detected, but test execution time and setup requirements increase

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidtest execution time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent employs periodic action through repeated simultaneous executions of testcases at varying speeds. By periodically executing the same testcases with different speed combinations, the system increases the probability of encountering the precise system states that reveal interaction defects. This periodic variation in execution parameters allows defects to be detected more quickly than would be possible with single, carefully-timed breakpoint-based executions.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11194701B2Identifying software interaction defects using differential speed processors
Publication Date: 2021.12.07 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11194701B2 patent drawing
  • US11194701B2 patent drawing
  • US11194701B2 patent drawing

AI summary

Aspects of the invention include methods, systems and computer program products for identifying interaction software defects. Aspects include singly executing a first testcase at a normal processing speed and singly executing a second testcase at the normal processing speed. Aspects also include simultaneously executing the first testcase at a first processing speed and a second testcase at a second processing speed. Based on determining the single and simultaneous testcase results do not match, aspects further include creating an error notification.