Differential Stress Control Liners for Transistor Performance
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Solution Overview
Problem
Existing semiconductor technologies face challenges in providing optimal stress conditions for p-type and n-type field effect transistors, as different types require specific stress levels to achieve optimal performance, which current methods fail to efficiently manage without increasing processing costs and time.
Innovation Solution
The implementation of a semiconductor structure featuring a silicon nitride liner and a thermal silicon oxide liner, where the upper portion of the silicon nitride liner is converted into thermal silicon oxide, allowing for controlled etching to provide different stress levels to p-type and n-type field effect transistors, optimizing channel stress and mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different stress control liners are used for p-type and n-type field effect transistors, then optimal stress conditions and performance are achieved, but processing complexity and time increase
Solution Approach 1:
The continuous silicon nitride liner is segmented into two distinct regions: a first region over the p-type transistor and a second region over the n-type transistor. This segmentation allows each region to provide different stress conditions tailored to the specific transistor type, optimizing performance without requiring completely separate liner structures for each device type.
Solution Approach 2:
Different portions of the silicon nitride liner are converted to silicon oxide in different regions. Specifically, the liner over the p-type transistor is converted to silicon oxide while the liner over the n-type transistor remains as silicon nitride. This local differentiation provides the appropriate stress characteristics (compressive for p-type, tensile for n-type) in each local region without affecting other areas.
2Reliability
If different stress control liners are used for p-type and n-type field effect transistors, then optimal stress conditions and performance are achieved, but processing time increases
Solution Approach 1:
The patent combines multiple functions into a single continuous silicon nitride liner structure. Instead of depositing separate liners for p-type and n-type transistors at different times, a single continuous liner is deposited and then selectively converted in different regions. This merging approach reduces the number of deposition steps while still achieving differentiated stress control.
Solution Approach 2:
The patent changes the material parameter of the stress control liner from uniform silicon nitride to a differentiated structure where portions are converted to silicon oxide. This parameter change (material composition) is achieved through selective thermal oxidation or chemical vapor deposition processes that convert silicon nitride to silicon oxide in specific regions, allowing different stress properties without adding entirely new liner layers.
3Ease of manufacture
If a continuous silicon nitride liner is used over both transistor types, then processing is simplified, but optimal stress conditions for both p-type and n-type transistors cannot be achieved
Solution Approach 1:
The continuous silicon nitride liner maintains processing simplicity, but local quality is introduced by converting portions of the liner to silicon oxide in different regions. The liner over the p-type transistor is converted to silicon oxide to provide compressive stress, while the liner over the n-type transistor remains as silicon nitride to provide tensile stress. This local differentiation achieves optimal stress conditions while maintaining the simplicity of a single continuous liner structure.
Solution Approach 2:
The patent changes the material parameter (composition) of the liner in different regions through selective conversion processes. By converting silicon nitride to silicon oxide in specific regions, the stress properties of the liner are modified locally without changing the overall continuous structure, thus maintaining processing simplicity while achieving differentiated performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables minimal increase in processing costs and time while effectively providing optimal stress conditions for both p-type and n-type transistors, enhancing their performance by tuning stress levels in the semiconductor channels.
Implementation Method 1
converting an upper portion of the silicon nitride liner into a thermal silicon oxide liner
Data Source
AI summary
A first field effect transistor and a second field effect transistor are formed on a substrate. A silicon nitride liner is formed over the first field effect transistor and the second field effect transistor. An upper portion of the silicon nitride liner is converted into a thermal silicon oxide liner. A lower portion of the silicon nitride liner remains as a silicon nitride material portion. A first portion of the thermal silicon oxide liner is removed from above the second field effect transistor, and a second portion of the thermal silicon oxide liner remains above the first field effect transistor. Selective presence of the silicon oxide liner provides differential stress within the channels of the first and second field effect transistors, which can be employed to optimize performance of different types of field effect transistors.