Differential Switch Reset Topology for Low-Distortion D/A Conversion
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Solution Overview
Problem
Conventional current switches in D/A converters for high-speed communications suffer from voltage fluctuations at the common source node, which degrade distortion characteristics due to drain conductance of transistors, leading to noise dependency on input digital codes.
Innovation Solution
A differential switch circuit with parallel first and second differential switch basic circuits, where common source nodes are alternately reset to a predetermined voltage in each clock cycle, preventing voltage fluctuations from affecting output currents and improving distortion characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional current switches are used in D/A converters, then the circuit structure is simple, but voltage fluctuations at the common source node occur due to drain conductance, degrading distortion characteristics
Solution Approach 1:
The differential switch is divided into two separate differential switch basic circuits operating in parallel, each handling alternating clock cycles. This segmentation isolates the voltage fluctuations in each basic circuit, preventing them from affecting the overall output and improving distortion characteristics while maintaining reasonable circuit complexity
Solution Approach 2:
The two differential switch basic circuits operate alternately in a periodic manner synchronized with the clock signal. One basic circuit operates during even clock cycles while the other operates during odd clock cycles, ensuring continuous current switching while allowing each circuit to reset periodically, thereby eliminating voltage fluctuations at common source nodes
2Duration of action of moving object
If the common source node voltage is not reset, then the circuit operation is continuous, but voltage fluctuations affect output currents and degrade distortion characteristics
Solution Approach 1:
Each differential switch basic circuit is provided with a reset mechanism that proactively resets the common source node voltage to a predetermined level before the next switching operation begins. This preliminary resetting action prevents voltage fluctuations from accumulating and affecting the output current, thereby improving distortion characteristics while maintaining continuous operation through the alternate operation of two basic circuits
Data Source
AI summary
A differential switch circuit includes a first differential switch basic circuit (1) and a second differential switch basic circuit (2). The first differential switch basic circuit (1) has a first common source node (N1) shared by a plurality of transistors (TP121 and TP122), and the second differential switch basic circuit (2) has a second common source node (N2) shared by a plurality of transistors (TP131 and TP132). The first common source node (N1) and the second common source node (N2) are alternately reset to a predetermined voltage in each clock cycle.