Differential Non-Volatile Synapse Arrays for Low-Power Accurate Computing
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Solution Overview
Problem
Conventional neural network circuits require high computational resources and suffer from power inefficiencies due to the need for frequent data transfer between CMOS logic and non-volatile memory, leading to unwanted program disturbances and degradation of computation accuracy.
Innovation Solution
Implementing a neural network with logic-friendly non-volatile synapses using a differential architecture that includes select transistors and logic-friendly NVM, minimizing parasitic resistance and sneak currents, and performing matrix multiplication within the synapse circuit using analog values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data is transferred frequently between CMOS logic and non-volatile memory, then computation can be performed, but power consumption increases and program disturbances occur
Solution Approach 1:
The patent merges the storage function and computation function into a single integrated structure by embedding non-volatile memory cells directly within the synapse array. This allows weight parameters to be stored and used for computation simultaneously, eliminating the need for frequent data transfer between separate memory and logic units, thereby reducing power consumption while maintaining computation accuracy.
Solution Approach 2:
The patent introduces select transistors as intermediary elements that control access to individual synapses within the array. These transistors enable precise selection of specific memory cells for computation while isolating others, preventing program disturbances to unselected cells and reducing overall power consumption by activating only necessary circuit elements.
2Quantity of substance
If separate off-chip non-volatile memory is used to store weight parameters, then storage capacity is sufficient, but power is wasted and latency increases due to data transfer
Solution Approach 1:
The patent implements a nested structure where non-volatile memory cells are embedded within the synapse array architecture. The memory cells are nested inside the computational fabric, allowing weight parameters to be stored in-place within the computation unit. This eliminates the need for separate off-chip memory, reducing power consumption associated with data transfer while maintaining sufficient storage capacity for all weight parameters.
Solution Approach 2:
The integrated synapse array serves multiple functions simultaneously: it stores weight parameters, performs computation operations, and provides selective access control. This multi-functional design eliminates the need for separate dedicated memory and computation units, improving power efficiency by keeping all functions within a single on-chip structure.
3Ease of manufacture
If conventional synaptic circuits are used, then implementation is straightforward, but parasitic resistance and sneak currents degrade computation accuracy
Solution Approach 1:
The patent applies local quality by making the synapse circuit asymmetric, with the non-volatile memory element positioned in a specific configuration relative to the select transistor. This asymmetric local arrangement optimizes the current path to minimize parasitic resistance effects and prevent sneak currents from affecting the computation, while the overall structure remains manufacturable using standard processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces computational complexity and power consumption while maintaining computation accuracy by suppressing multiplication noise and compensating for quantization noise, resulting in a robust and efficient neural network operation.
Implementation Method 1
each cell comprising a non-volatile resistive changing element and a select transistor
Implementation Method 2
performing matrix multiplication within the synapse circuit using analog values
Data Source
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AI summary
A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: an input signal line (265); a reference signal line (264); first and second output lines (266 and 267), and first and second cells (332 and 334) for generating the first and second output signals, respectively. The first cell (332) includes: an upper select transistor (311) having a gate that is electrically coupled to the input signal line (265); and a resistive changing element (313) having one end connected to the upper select transistor (311) in series and another end electrically coupled to the reference signal line (264). The value of the resistive changing element (313) is programmable to change the magnitude of an output signal (203). The drain of the upper select transistor (311) of the first cell (332) is electrically coupled to the first output line (266) and the drain of the select transistor (312) of the second cell (334) is electrically coupled to the second output line (267).