Differential Tap Network for SerDes ISI Mitigation
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Solution Overview
Problem
Existing serializer/deserializer (SerDes) systems face challenges in effectively mitigating Intersymbol Interference (ISI) at high data speeds, particularly in PCIe Gen5 where channel loss and ISI errors are more pronounced.
Innovation Solution
The proposed solution involves a decision feedback equalization (DFE) circuit with a differential tap network architecture, where the sum amplifier includes at least one resistor, one transistor, and one source node directly connected to a complete tap network. This design maintains tap activity differentially, eliminating the need for a common mode feedback loop and improving tap settling times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional sum amplifier architecture is used with tap network, then the circuit can perform basic equalization function, but the bandwidth is limited and settling time is long
Solution Approach 1:
The patent divides the sum amplifier into two independent differential pairs: a first differential pair for processing positive tap currents and a second differential pair for processing negative tap currents. This segmentation allows each pair to operate independently with optimized bandwidth, eliminating the bottleneck of a single conventional sum amplifier and reducing settling time by parallel processing.
Solution Approach 2:
The patent transitions from a single-ended sum amplifier to a differential architecture, adding a second dimension of signal representation. By using differential pairs with separate positive and negative current paths, the circuit achieves higher bandwidth and faster settling time while maintaining common mode stability.
2Reliability
If a conventional sum amplifier architecture is used, then the circuit structure is simple, but common mode output stability deteriorates at high data speeds
Solution Approach 1:
The patent segments the common mode stabilization function into separate differential pairs that independently handle positive and negative currents. This segmentation allows the common mode to be stabilized through differential operation without requiring complex feedback mechanisms, achieving reliability while controlling complexity.
Solution Approach 2:
The patent implements implicit feedback through the differential pair architecture itself. The differential operation naturally compensates for common mode variations by comparing the two sides of the differential pair, providing self-regulating common mode stability without external feedback circuits.
3Reliability
If more taps are added to increase equalization capability, then ISI mitigation improves, but device complexity and power consumption increase
Solution Approach 1:
The patent segments the tap network into positive and negative current paths handled by separate differential pairs. This segmentation allows the system to accommodate more taps by distributing them across the differential structure, improving ISI mitigation capability while maintaining manageable complexity through modular differential processing.
Data Source
AI summary
The present disclosure relates to an apparatus and method for decision feedback equalization. Embodiments include a sum amplifier having a differential tap network architecture wherein the sum amplifier includes at least one resistor, at least one transistor, and at least one source node, wherein the at least one source node is directly connected to a complete tap network.