Differential Transmitter Circuit With Unified Pre-Driver Timing
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Solution Overview
Problem
LVDS transmitters face challenges in meeting tight timing constraints over process, voltage, and temperature (PVT) variations due to the need for multiple separate pre-driver signals to control current-steering switches, making it difficult to achieve high speed and robustness.
Innovation Solution
A pre-driver circuit with programmable slew rate controls only one pair of current-steering switches (NMOS transistors), while the other pair (PMOS transistors) is controlled by internal loopback signals, reducing the number of required pre-driver signals and simplifying timing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple separate pre-driver signals are used to control current-steering switches, then high-speed performance can be achieved, but timing constraints become difficult to meet over PVT variations
Solution Approach 1:
The patent merges the control of both PMOS and NMOS current-steering switches into a single pre-driver signal path. The unified differential output stage uses one pre-driver signal to simultaneously control both pairs of switches, eliminating the need for separate pre-driver signals and their associated timing constraints. This combining approach maintains high-speed performance while significantly improving reliability over PVT variations.
Solution Approach 2:
The single pre-driver signal performs multiple functions by controlling both PMOS and NMOS current-steering switches through a unified differential output stage. This multi-functional approach replaces the traditional separate control paths, reducing the number of timing-critical signal paths while maintaining the ability to drive both pull-up and pull-down currents effectively.
2Speed
If four separate pre-driver signals are used to control PMOS and NMOS switches, then output slew rate requirements can be met, but the number of required pre-driver signals increases complexity
Solution Approach 1:
The patent combines four separate pre-driver signals into a single unified pre-driver signal that controls both PMOS and NMOS current-steering switches. The differential output stage architecture enables this consolidation by using the single signal to generate complementary control voltages for both transistor pairs, thereby reducing device complexity while maintaining the required output slew rate for high-speed LVDS transmission.
3Speed
If tight timing constraints are imposed on pre-driver signals, then high-speed transmission can be achieved, but design robustness over PVT variations deteriorates
Solution Approach 1:
By merging the control paths into a single pre-driver signal, the patent reduces the number of timing-critical paths in the circuit. This consolidation eliminates the need for multiple synchronized signal paths, thereby maintaining high transmission speed while significantly improving robustness against process, voltage, and temperature variations that would otherwise cause timing violations.
4Manufacturing precision
If separate pre-driver circuits are used for PMOS and NMOS switches, then precise control can be achieved, but the design cycle extends due to increased complexity
Solution Approach 1:
The patent merges separate pre-driver circuits into a single unified pre-driver that controls both PMOS and NMOS switches through a differential output stage. This consolidation maintains precise control of the current-steering switches while dramatically reducing design complexity, thereby shortening the design cycle without sacrificing manufacturing precision.
Data Source
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AI summary
In an integrated circuit, a first current source is coupled between a first supply voltage and a first node. An output stage includes a first current steering PMOS transistor coupled to the first node, a first current steering NMOS transistor including a first current electrode coupled to the first current steering PMOS transistor at a second node, a second current steering PMOS coupled to the first node, and a second current steering NMOS transistor including a first current electrode coupled to the second current steering PMOS transistor at a third node. Voltage at the second node is used to drive a gate of the second current steering PMOS transistor, and voltage at the third node is used to drive a gate of the first current steering PMOS transistor. First and second programmable slew rate pre-drivers provide outputs to the gates of the first and second current steering NMOS transistors, respectively.