Differential VCO Buffer for Duty-Cycle Stability Under Supply Noise
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Solution Overview
Problem
Existing signal buffers for oscillators and phase locked loops (PLLs) face challenges in maintaining signal integrity and duty cycle stability, particularly under varying supply voltage conditions, which can lead to distortion and power inefficiency.
Innovation Solution
The proposed buffer design incorporates a first buffer stage with a configuration of field effect transistors (FETs) and capacitors, where the FETs are coupled in series between voltage rails, and the gates of specific FETs are coupled together or configured to receive differential signal components. This design includes capacitors and resistors to stabilize the signal and mitigate the effects of supply voltage noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a conventional buffer is used to amplify the clock signal, then the signal amplitude is boosted, but the duty cycle becomes distorted and the oscillator frequency shifts due to loading effects
Solution Approach 1:
The buffer is divided into multiple stages: a differential input stage with FETs M1-M4 that preserves duty cycle, followed by a push-pull output stage with FETs M5-M8 that provides full rail-to-rail swing. Each stage is optimized for its specific function, allowing amplitude boosting without duty cycle distortion.
Solution Approach 2:
The patent introduces intermediate differential signaling stages between the oscillator and final output buffer. These intermediate stages act as mediators that transfer the signal while maintaining duty cycle integrity, preventing the loading effects that would otherwise distort the oscillator frequency.
2Reliability
If a buffer is added to prevent loading of the oscillator, then the oscillator frequency stability is improved, but the overall circuit complexity increases
Solution Approach 1:
The buffer circuit performs multiple functions simultaneously: it provides impedance buffering to prevent loading, amplifies the signal to full rail-to-rail swing, and maintains duty cycle accuracy. By combining these functions in a unified multi-stage design, the patent avoids needing separate circuits for each function, thereby limiting the increase in complexity.
3Power
If the buffer operates with high gain to amplify the signal, then the output amplitude is sufficient for downstream circuits, but the circuit becomes more sensitive to supply voltage noise
Solution Approach 1:
The patent incorporates feedback mechanisms in the buffer stages, particularly in the push-pull output stage, to stabilize the output signal against supply voltage variations. The feedback loops actively compensate for noise and disturbances, maintaining signal integrity even at high gain settings.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively amplifies and stabilizes the input signal, maintaining a substantially 50% duty cycle and full rail-to-rail swing, while being immune to supply voltage noise, thus enhancing signal integrity and reducing power consumption.
Implementation Method 1
a first capacitor coupled between a drain of the second FET and the gates of the first and third FETs
Data Source
AI summary
An apparatus, including: a buffer configured to receive an input differential signal and generate an output signal based on the input differential signal, wherein the buffer includes a first buffer stage including: a first field effect transistor (FET); a second FET coupled in series with the first FET between a first voltage rail and a second voltage rail; a third FET; a fourth FET coupled in series with the third FET between the first voltage rail and the second voltage rail, wherein the first and third FETs include gates coupled together, and wherein the second and fourth FETs include gates configured to receive positive and negative components of the input differential signal; and a first capacitor coupled between a drain of the second FET and the gates of the first and third FETs.