Differential Wake-Up Receiver Using Cross-Coupled NMOS Input
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Solution Overview
Problem
Existing wake-up receivers for CAN systems face challenges in detecting wake-up signals at low supply voltages, especially in environments with high RF common mode noise, due to the minimum supply requirements of BJTs and diodes.
Innovation Solution
A differential input receiver is designed with a cross-coupled differential amplifier as the input stage, utilizing NMOS FETs and resistive dividers to attenuate common mode voltages and provide sufficient gain for wake-up signal detection at low supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BJTs and diodes are used in wake-up receivers, then the receiver can detect wake-up signals, but the minimum supply voltage requirement increases
Solution Approach 1:
The patent changes the device parameters by replacing BJT and diode components with NMOS FET-based differential amplifier circuitry. This parameter change allows the wake-up receiver to operate at lower supply voltages (below 1.2V) while maintaining wake-up signal detection capability, directly resolving the contradiction between detection reliability and power consumption.
2Productivity
If conventional receiver designs are used, then the circuit can operate, but electromagnetic compatibility in high RF common mode noise environments deteriorates
Solution Approach 1:
The patent converts the harmful high RF common mode noise into a beneficial effect by using the common mode voltage itself to bias the NMOS FET gates through source-gate feedback connections. This allows the circuit to reject differential wake-up signals while operating in high common mode noise environments, improving electromagnetic compatibility without sacrificing functionality.
Solution Approach 2:
The patent introduces voltage divider networks as intermediary elements that attenuate the high common mode voltage before it reaches the sensitive differential amplifier stage. These intermediaries protect the circuit from harmful RF noise while allowing the differential signal to pass through, resolving the contradiction between operational functionality and electromagnetic compatibility.
3Productivity
If wake-up receivers operate in high common mode noise environments, then they can function, but signal detection precision decreases
Solution Approach 1:
The patent employs asymmetric circuit configuration where the NMOS FETs are connected with source-gate feedback to create different impedance paths for common mode and differential mode signals. This asymmetry allows the circuit to maintain high detection precision for differential wake-up signals while rejecting common mode noise, resolving the contradiction between operational functionality and measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reliable wake-up signal detection at low power supply and high common mode noise conditions, achieving excellent electromagnetic compatibility and low quiescent current consumption.
Implementation Method 1
utilizing NMOS FETs and resistive dividers to attenuate common mode voltages
Implementation Method 2
A differential input receiver is designed with a cross-coupled differential amplifier as the input stage, utilizing NMOS FETs and resistive dividers to attenuate common mode voltages and provide sufficient gain for wake-up signal detection at low supply voltages
Data Source
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Figure 2
AI summary
A differential input receiver for detecting wake-up signalling in a differential communication system. The receiver has a first and a second diode connected FET. The source of the first diode connected FET is connected to a positive input signal terminal. The drain of the first diode connected FET is connected to a first current source. The gate of the first diode connected FET is connected to the first current source. The source of the second diode connected FET is connected to a negative input signal terminal. The drain of the second diode connected FET is connected to a second current source. The gate of the second diode connected FET is connected to the second current source. The receiver also included a first and a second cross differential FET. The source of the first cross differential FET is connected to the negative input signal terminal. The drain of the first cross differential FET is connected to a first output terminal. The gate of the first cross differential FET is connected to the gate of the first diode connected FET. The source of the second cross differential FET is connected to the positive input signal terminal. The drain of the second cross differential FET is connected to a second output terminal. The gate of the second cross differential FET is connected to the gate of the second diode connected FET.