Differential Write Clock Signal Overlapping Memory Access
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Solution Overview
Problem
Memory systems face increased access switching time and power consumption when switching between different memory chips due to the need for synchronization of separate clock inputs, which hinders performance and efficiency in applications like VR, AR, and AI.
Innovation Solution
Employing a differential write clock signal as two single-ended clock signals, allowing independent control of read and write operations across memory chips, thereby enabling overlapping of write clock signal operations and reducing the need for continuous clocking and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate clock inputs are used for each memory chip, then each memory chip can be independently controlled, but access switching time increases and power consumption increases due to synchronization requirements
Solution Approach 1:
The patent merges the clock inputs by providing a single clock signal that is distributed to multiple memory chips. This single clock signal replaces multiple separate clock inputs, allowing memory chips to be controlled in a coordinated manner rather than requiring separate synchronized clock signals for each chip.
Solution Approach 2:
The single clock input serves multiple functions by being distributed to multiple memory chips simultaneously. This universal clock signal enables coordinated control across all memory chips in the stack, eliminating the need for separate clock synchronization mechanisms.
2Ease of operation
If separate clock inputs are used for each memory chip, then each memory chip can be independently controlled, but power consumption increases due to continuous clocking requirements
Solution Approach 1:
The patent merges the clock inputs by providing a single clock signal that is distributed to multiple memory chips. This single clock signal replaces multiple separate clock inputs, allowing memory chips to be controlled in a coordinated manner rather than requiring separate synchronized clock signals for each chip.
Solution Approach 2:
The system uses periodic clock signals that can be synchronized across memory chips, allowing idle memory chips to enter low-power states when not actively being accessed, thereby reducing overall power consumption while maintaining independent control capability.
3Device complexity
If multiple memory chips share a common bus, then device complexity is reduced, but access switching time increases due to synchronization requirements
Solution Approach 1:
The patent merges the clock inputs by providing a single clock signal that is distributed to multiple memory chips. This single clock signal replaces multiple separate clock inputs, allowing memory chips to be controlled in a coordinated manner rather than requiring separate synchronized clock signals for each chip.
Solution Approach 2:
The system performs preliminary synchronization of the single clock signal across all memory chips before access operations begin. This preliminary action ensures that all memory chips are ready to operate in coordination, reducing the switching time when accessing different chips in the stack.
4Reliability
If synchronization is performed between memory chips, then coordinated access is achieved, but access switching time and power consumption increase
Solution Approach 1:
The patent merges the clock inputs by providing a single clock signal that is distributed to multiple memory chips. This single clock signal replaces multiple separate clock inputs, allowing memory chips to be controlled in a coordinated manner rather than requiring separate synchronized clock signals for each chip.
Solution Approach 2:
The system performs preliminary synchronization of the single clock signal across all memory chips before access operations begin. This preliminary action ensures that all memory chips are ready to operate in coordination, reducing the switching time when accessing different chips in the stack.
Data Source
AI summary
Improved methods and systems for accessing a memory in a computer are disclosed. In one embodiment, the true and complement portions of a differential write clock signal are employed as two single ended clock signals for independently controlling different memory chips in a memory system. For example, in a memory system having two memory chips, one memory chip is configured to use the true write clock signal and the other memory chip is configured to use the complement write clock signal. Employing the differential write clock signal as two single ended clock signals allows overlapping of write and read operations across multiple memory chips, reducing the time needed for accessing memory. Accordingly, the disclosed methods and systems provide a more efficient memory system that can be used to improve the operation of a computer.