Differentiated QOS in Parallel Cached RAS Channels
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Solution Overview
Problem
Conventional memory devices face challenges in efficiently implementing reliability, availability, and serviceability (RAS) features, particularly when multiple memory media devices are connected, leading to issues like increased error detection time and reduced link bandwidth due to the inability to control ECC granularity in narrow channels like LPDDR5.
Innovation Solution
The implementation of RAS channel data path arrangements with differentiated quality of service (QoS) and dedicated RAS controllers for each group of memory media, along with cache arrangements to improve responsiveness and reduce congestion by allowing finer granularity throttling and virtual channel management, enabling efficient error correction and data access across multiple memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory media devices are connected to the same memory device, then storage capacity and parallelism are improved, but error detection time increases and link bandwidth is reduced
Solution Approach 1:
The patent divides the error correction system into separate RAS channels, with each channel dedicated to a specific memory media device. This segmentation allows independent error detection and correction for each device, preventing errors in one device from affecting others and reducing overall error detection time despite having multiple devices connected.
2Productivity
If multiple memory media devices are connected to the same memory device, then storage capacity and parallelism are improved, but link bandwidth is reduced
Solution Approach 1:
The patent implements separate RAS channels for each memory media device, allowing independent error correction operations. This segmentation enables parallel error correction across multiple devices without sharing bandwidth, maintaining link bandwidth for each device while supporting multiple devices for increased storage capacity.
3Ease of operation
If ECC granularity is not controllable in narrow channels like LPDDR5, then data transfer simplicity is maintained, but error correction efficiency is reduced
Solution Approach 1:
The patent provides differentiated quality of service (QoS) for each RAS channel, allowing fine-grained control of error correction parameters specific to each memory media device. This local quality control enables optimized error correction efficiency for each device type while maintaining the simplicity of the overall data transfer mechanism through standardized channel interfaces.
4Device complexity
If a single RAS controller is used for multiple memory media devices, then device complexity is reduced, but RAS capability and responsiveness are limited
Solution Approach 1:
The patent implements separate RAS controllers for each memory media device, with each controller dedicated to managing RAS operations for its associated device. This segmentation provides dedicated RAS capability for each device, improving reliability and responsiveness while keeping each individual controller simple and manageable.
5Speed
If cache arrangements are added to improve responsiveness, then data access speed is improved, but device complexity increases
Solution Approach 1:
The patent introduces cache arrangements as intermediary storage between the memory media devices and the processing system. Each RAS channel has its own cache, acting as a mediator that stores frequently accessed data to improve responsiveness. This intermediary approach increases speed while managing complexity by keeping each cache associated with its specific RAS channel for independent control.
Data Source
AI summary
A memory device comprises a plurality of backend interfaces that are each configured to connect to a respective media device (e.g., DDR, LPDDR DRAM), a plurality of reliability, availability and serviceability (RAS) channel datapaths with each RAS channel datapath connected to one or more backend interfaces, one or more caches that are each connected to at least one RAS channel datapath, and control circuitry. The control circuitry is configured to: in response to receiving a memory access request for a memory location, search a cache of the one or more caches for the requested memory location; and when, in response to the search, the requested memory location is not found in the cache, obtain the requested memory location from a media device connected to the at least one RAS channel datapath. Corresponding methods are also described.