Diffused Cap Layers for High-k Gate Dielectric Interface Control
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Solution Overview
Problem
The integration of metal gate electrodes with high-k gate dielectrics in NMOS and PMOS devices faces challenges such as polysilicon gate depletion, high gate resistance, and instability in threshold voltage due to the regrowth of silicon oxide interface layers during high-temperature processing, which complicates effective oxide thickness scaling and device performance optimization.
Innovation Solution
A method involving the use of cap layers with specific chemical elements to diffuse into the high-k film, scavenging oxygen and modifying the interface layer, thereby reducing or eliminating the silicon oxide interface layer, allowing for the deposition of a gate electrode film that sets appropriate work functions near the silicon band edges for improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-k gate dielectric materials are used to scale down effective oxide thickness, then gate leakage current is reduced, but silicon oxide interface layer regrowth occurs during high-temperature processing
Solution Approach 1:
A cap layer containing aluminum or gallium is introduced as an intermediary between the high-k gate dielectric and the silicon substrate. This cap layer acts as an oxygen sink during high-temperature processing, preventing oxygen from the silicon substrate from diffusing into the high-k dielectric and forming silicon oxide interface layers. The cap layer absorbs the harmful oxygen, thereby maintaining threshold voltage stability while allowing the use of thin high-k dielectrics for reduced gate leakage.
2Length of moving object
If high-k gate dielectric is used with thin interface layer, then effective oxide thickness scaling is enabled, but interface layer regrowth occurs during high-temperature anneal in oxygen ambient
Solution Approach 1:
The cap layer serves as a protective intermediary that prevents oxygen from the processing ambient and silicon substrate from reaching the high-k dielectric interface during high-temperature annealing. This intermediary layer allows manufacturers to maintain precisely controlled thin interface layers without the risk of regrowth, enabling effective oxide thickness scaling while maintaining manufacturing precision.
Solution Approach 2:
The process involves changing the chemical composition parameter by introducing a cap layer with specific elements (aluminum or gallium) that have high affinity for oxygen. This parameter change transforms the system's behavior during thermal processing, preventing unwanted oxidation reactions at the high-k dielectric interface while maintaining the desired thin interface layer thickness.
3Adaptability or versatility
If separate gate electrode layers are formed to obtain differentiated work functions, then NMOS and PMOS work function requirements are met, but gate insulator layer is damaged leading to high leakage
Solution Approach 1:
The cap layer is formed preliminarily before depositing the gate electrode layers. This preliminary action of placing the oxygen-scavenging cap layer protects the gate insulator from damage during subsequent processing steps. By establishing this protective layer first, the process enables work function differentiation through multiple gate electrode layers without causing gate insulator damage and associated leakage problems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a gate stack with reduced or zero interface layer thickness, enhancing the scalability and performance of field effect transistors by maintaining stable threshold voltage and optimizing drain current, while simplifying the gate etch process with uniform stack heights for both NMOS and PMOS devices.
Implementation Method 1
performing a heat-treating process to diffuse the first chemical element into the high-k film in the NMOS device region
Implementation Method 2
reduce or eliminate the interface layer by oxygen diffusion from the interface layer through the high-k film into the second cap layer
Implementation Method 3
reduce or eliminate the interface layer by oxygen diffusion from the interface layer through the high-k film into the second cap layer
Implementation Method 4
performing a heat-treating process to diffuse the first chemical element into the high-k film in the NMOS device region and to reduce or eliminate the interface layer by oxygen diffusion
Data Source
AI summary
Method of forming a semiconductor device includes providing a substrate with defined NMOS and PMOS device regions and an interface layer on the NMOS and PMOS device regions, depositing a high-k film on the interface layer, depositing a first cap layer on the high-k film, and removing the first cap layer from the high-k film in the PMOS device region. The method further includes depositing a second cap layer on the first cap layer in the NMOS device region and on the high-k film in the PMOS device region, performing a heat-treating process to diffuse a first chemical element into the high-k film in the NMOS device region and to reduce or eliminate the interface layer by oxygen diffusion from the interface layer into the second cap layer, removing the first and second cap layers from the high-k film, and depositing a gate electrode film over the high-k film.