Diffusion Barrier Layer for High-k Gate Insulation
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Solution Overview
Problem
Semiconductor devices with high-k gate insulation layers experience increased threshold voltage and decreased electron mobility due to the Fermi-level pinning effect when a polysilicon gate electrode is formed directly on these layers, leading to suboptimal transistor performance.
Innovation Solution
A diffusion barrier layer and a diffusion layer, comprising materials like lanthanum or aluminum, are introduced to selectively diffuse elements into the high-k dielectric material of the gate insulation layer, followed by a thermal annealing process to reduce leakage current and threshold voltage, while preventing excessive diffusion and maintaining electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polysilicon gate electrode is formed directly on the high-k gate insulation layer, then the gate insulation layer provides effective insulation, but the transistor experiences increased threshold voltage and decreased electron mobility due to Fermi-level pinning
Solution Approach 1:
A diffusion barrier layer is introduced as an intermediary between the polysilicon gate electrode and the high-k gate insulation layer. This barrier layer prevents direct contact between the polysilicon and high-k material, thereby eliminating the Fermi-level pinning effect while maintaining the insulation functionality of the gate insulation layer.
Solution Approach 2:
The gate structure is segmented into multiple distinct layers: the high-k gate insulation layer, the diffusion barrier layer, and the polysilicon gate electrode. This segmentation allows each layer to perform its specific function independently, with the barrier layer specifically addressing the Fermi-level pinning issue without compromising the insulation properties.
2Object-generated harmful factors
If a diffusion barrier layer is formed on the gate insulation layer, then the Fermi-level pinning effect is prevented, but the device structure becomes more complex
Solution Approach 1:
The patent specifies particular material compositions and thickness ranges for the diffusion barrier layer (e.g., tungsten, titanium, or their nitrides with thicknesses of 1-10 nm) to optimize its effectiveness in preventing Fermi-level pinning while minimizing the added structural complexity. By controlling these parameters, the barrier layer achieves its function with minimal impact on overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current and threshold voltage in NMOS transistors and maintains electron mobility, improving the operational speed and performance of semiconductor devices by preventing the Fermi-level pinning effect and minimizing diffusion-related issues.
Implementation Method 1
diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region
Implementation Method 2
performing a thermal annealing process on the substrate to diffuse the element of the diffusion layer into the first portion of the gate insulation layer
Implementation Method 3
forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region
Data Source
AI summary
Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region.