Diffusion Barrier Layer for Semiconductor Wafer Annealing
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Solution Overview
Problem
High temperature annealing processes in semiconductor wafer processing often lead to counter-doping due to the out-diffusion of volatile dopant atoms, which can alter the resistance of low-doped regions and cause integrated circuits to fail, especially when the silicon nitride barrier is damaged or defective.
Innovation Solution
Encapsulating the semiconductor wafer with a diffusion barrier layer, such as silicon nitride or silicon oxynitride, prior to high temperature annealing, and removing it afterward, along with increasing the oxide thickness on the topside to compensate for potential losses during stripping, helps prevent counter-doping and ensures accurate dopant concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon nitride barrier layer is used to prevent dopant out-diffusion, then counter-doping is prevented, but the layer may be damaged by scratches or defects causing dopant leakage
Solution Approach 1:
The patent applies local quality by creating different barrier structures at different locations. A first oxide layer is formed on the front surface while a silicon nitride layer is formed on the back surface, providing location-specific protection tailored to the local doping requirements and damage risks at each surface
Solution Approach 2:
The patent uses composite materials by combining oxide layers and silicon nitride layers in a multi-layer structure. This composite approach leverages the complementary properties of each material - the oxide provides a stable base layer while the silicon nitride provides superior dopant barrier properties, creating a more robust combined protection system
2Reliability
If a diffusion barrier layer is deposited on the topside, then counter-doping is prevented, but oxide thickness may be reduced during stripping affecting subsequent processing
Solution Approach 1:
The patent applies preliminary action by forming the first oxide layer on the front surface before depositing the diffusion barrier layer. This pre-formed oxide layer serves as a sacrificial layer that protects the underlying critical oxide structures during the barrier layer deposition and subsequent stripping processes, ensuring precise control of the final oxide thickness
Solution Approach 2:
The patent uses beforehand cushioning by creating the first oxide layer as a protective cushion before the barrier layer is deposited. This cushion layer absorbs the mechanical stress and potential damage during barrier layer formation and stripping, preventing direct damage to the critical underlying oxide structures and maintaining manufacturing precision
3Manufacturing precision
If high temperature anneal is performed to form diffused wells, then desired doping profiles are achieved, but volatile dopant atoms out-diffuse causing counter-doping
Solution Approach 1:
The patent introduces intermediary barrier layers (oxide layers and silicon nitride layers) between the highly doped substrate regions and the lightly doped epitaxial regions. These intermediary layers act as mediators that block the direct diffusion path of volatile dopant atoms during high temperature annealing, preventing counter-doping while allowing the desired doping profiles to form in the target regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents counter-doping during high temperature annealing, ensuring the integrity of integrated circuits by maintaining precise dopant concentrations and reducing particle and defect issues, thereby enhancing the yield of integrated circuits.
Implementation Method 1
Encapsulating the semiconductor wafer with a diffusion barrier layer, such as silicon nitride or silicon oxynitride, prior to high temperature annealing
Implementation Method 2
Silicon nitride is an effective barrier to volatile dopants such as boron and phosphorus
Data Source
AI summary
In a described example method, semiconductor wafer with a backside silicon nitride layer is encapsulated with a diffusion barrier layer prior to a high temperature anneal greater than about 1000 degrees Celsius. After the high temperature anneal the diffusion barrier layer and the backside silicon nitride layers are stripped.