Diffusion Break Material for Backside Power Rail CMP

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Solution Overview

Problem

The existing semiconductor device manufacturing processes face challenges in backside power rail formation due to over-polishing and under-etching issues during chemical mechanical planarization (CMP) without an etch stop layer, leading to shorts or open vias, which affects the reliability and efficiency of transistor devices.

Innovation Solution

The introduction of a diffusion break material as a planarization stop for backside power rail formation in gate-all-around (GAA) devices, which serves as an effective etch stop layer during the CMP process, reducing the height and aspect ratio of via openings and improving the precision of the BPR-via etch and fill process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If CMP process is performed without an etch stop layer, then wafer thickness is reduced for backside power rail formation, but over-polishing occurs leading to manufacturing precision deterioration

Engineering Contradiction:
Improvewafer thicknessVSAvoidwafer thickness control
Core Design Contradiction:
Length of stationary objectVSManufacturing precision

Solution Approach 1:

An etch stop layer is formed on the front surface of the wafer before the CMP process. This preliminary action creates a reference surface that prevents over-polishing during backside thinning, ensuring precise thickness control while enabling thinning to the required extent.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etch stop layer acts as an intermediary between the CMP polishing surface and the active device regions. It provides a mechanical stop that prevents the polishing head from removing too much material, thereby maintaining manufacturing precision during the thickness reduction process.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If via-etch is performed through silicon from backside without an etch stop layer, then access to source-epi is achieved, but over-etching occurs leading to shorts

Engineering Contradiction:
Improvevia-etch accessibilityVSAvoidshort prevention
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The etch stop layer is deposited on the front surface before backside via-etching. This preliminary action creates a protective barrier that prevents etching from penetrating through the substrate and causing shorts between front and backside metallization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etch stop layer serves as an intermediary barrier during the via-etch process. It allows the etch to proceed through the silicon substrate to access the source-epi region while simultaneously preventing excessive etching that would create conductive paths and cause shorts.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If via-etch is performed without an etch stop layer, then access to source-epi is achieved, but under-etching occurs leading to open circuits

Engineering Contradiction:
Improvevia-etch accessibilityVSAvoidvia depth control
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The etch stop layer provides a physical feedback mechanism during the via-etch process. When the etch front reaches the etch stop layer, the etching rate changes or stops, providing inherent feedback that prevents under-etching and ensures precise via depth control for reliable electrical contact.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The diffusion break material enhances the accuracy and reliability of backside power rail formation by preventing over-etching and under-etching, thereby improving the structural integrity and performance of semiconductor devices.

Implementation Method 1

the wafer thickness is reduced after front-side processing using a chemical mechanical planarization (CMP) process without an etch stop layer

Methodology Applied
Scientific EffectChemical mechanical planarization (CMP):

Implementation Method 2

The introduction of a diffusion break material as a planarization stop for backside power rail formation in gate-all-around (GAA) devices, which serves as an effective etch stop layer during the CMP process

Methodology Applied
Scientific EffectEtch stop layer effect:

Data Source

PatentUS20230260909A1Gate all around backside power rail with diffusion break
Publication Date: 2023.08.17 APPLIED MATERIALS INC
  • US20230260909A1 patent drawing
  • US20230260909A1 patent drawing
  • US20230260909A1 patent drawing

AI summary

Semiconductor devices and methods of manufacturing the same are described. The method includes forming a diffusion break opening on the backside and filling with a diffusion break material to serve as a planarization stop. In some embodiments, a single diffusion break opening is formed. In other embodiments, a mixed diffusion break opening is formed.